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AD8361ARM Fiches technique(PDF) 5 Page - Analog Devices |
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AD8361ARM Fiches technique(HTML) 5 Page - Analog Devices |
5 / 24 page AD8361 Rev. C | Page 5 of 24 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS VPOS 1 IREF 2 RFIN 3 PWDN 4 SREF 8 VRMS 7 FLTR 6 COMM 5 AD8361 TOP VIEW (Not to Scale) Figure 4. 8-Lead MSOP VRMS 1 COMM 2 FLTR 3 VPOS 6 RFIN 5 PWDN 4 AD8361 TOP VIEW (Not to Scale) Figure 5. 6-Lead SOT-23 Table 3. Pin Function Descriptions Pin No. MSOP Pin No. SOT-23 Mnemonic Description 1 6 VPOS Supply Voltage Pin. Operational range 2.7 V to 5.5 V. 2 N/A IREF Output Reference Control Pin. Internal reference mode enabled when pin is left open; otherwise, this pin should be tied to VPOS. Do not ground this pin. 3 5 RFIN Signal Input Pin. Must be driven from an ac-coupled source. The low frequency real input impedance is 225 Ω. 4 4 PWDN Power-Down Pin. For the device to operate as a detector, it needs a logical low input (less than 100 mV). When a logic high (greater than VS − 0.5 V) is applied, the device is turned off and the supply current goes to nearly zero (ground and internal reference mode less than 1 µA, supply reference mode VS divided by 100 kΩ). 5 2 COMM Device Ground Pin. 6 3 FLTR By placing a capacitor between this pin and VPOS, the corner frequency of the modulation filter is lowered. The on-chip filter is formed with 27 pF||2 kΩ for small input signals. 7 1 VRMS Output Pin. Near rail-to-rail voltage output with limited current drive capabilities. Expected load >10 kΩ to ground. 8 N/A SREF Supply Reference Control Pin. To enable supply reference mode, this pin must be connected to VPOS; otherwise, it should be connected to COMM (ground). |
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