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AD5338BRMZ-1REEL7 Fiches technique(PDF) 4 Page - Analog Devices

No de pièce AD5338BRMZ-1REEL7
Description  2.5 V to 5.5 V, 250 muA, 2-Wire Interface
Download  28 Pages
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Fabricant  AD [Analog Devices]
Site Internet  http://www.analog.com
Logo AD - Analog Devices

AD5338BRMZ-1REEL7 Fiches technique(HTML) 4 Page - Analog Devices

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AD5337/AD5338/AD5339
Rev. C | Page 4 of 28
A Grade1
B Grade1
Parameter2
Min
Typ
Max
Min
Typ
Max
Unit
Conditions/Comments
LOGIC INPUTS (A0)5
Input Current
±1
±1
μA
Input Low Voltage (VIL)
0.8
0.8
V
VDD = 5 V ± 10%
0.6
0.6
V
VDD = 3 V ± 10%
0.5
0.5
V
VDD = 2.5 V
Input High Voltage (VIH)
2.4
2.4
V
VDD = 5 V ± 10%
2.1
2.1
V
VDD = 3 V ± 10%
2.0
2.0
V
VDD = 2.5 V
Pin Capacitance
3
3
pF
LOGIC INPUTS (SCL, SDA)5
Input High Voltage (VIH)
0.7 ×
VDD
VDD +
0.3
0.7 ×
VDD
VDD +
0.3
V
SMBus compatible at
VDD < 3.6 V
Input Low Voltage (VIL)
−0.3
+0.3
VDD
–0.3
+0.3
VDD
V
SMBus compatible at
VDD < 3.6 V
Input Leakage Current (IIN)
±1
±1
μA
Input Hysteresis (VHYST)
0.05 ×
VDD
0.05 ×
VDD
V
Input Capacitance (CIN)
8
8
pF
Glitch Rejection
50
50
ns
Input filtering suppresses
noise spikes of less than
50 ns
LOGIC OUTPUT (SDA)5
Output Low Voltage (VOL)
0.4
0.4
V
ISINK = 3 mA
0.6
0.6
V
ISINK = 6 mA
Three-State Leakage Current
±1
±1
μA
Three-State Output Capacitance
8
8
pF
POWER REQUIREMENTS
VDD
2.5
5.5
2.5
5.5
V
IDD (Normal Mode)7
VIH = VDD and VIL = GND
VDD = 4.5 V to 5.5 V
300
375
300
375
μA
VDD = 2.5 V to 3.6 V
250
350
250
350
μA
IDD (Power-Down Mode)
VIH = VDD and VIL = GND
VDD = 4.5 V to 5.5 V
0.2
1.0
0.2
1.0
μA
IDD = 4 μA (max) during 0
readback on SDA
VDD = 2.5 V to 3.6 V
0.08
1.00
0.08
1.00
μA
IDD = 1.5 μA (max) during 0
readback on SDA
1 Temperature range for A Version and B Version: −40°C to +105°C; typical at 25°C.
2 See the Terminology section for explanations of the specific parameters.
3 DC specifications tested with the outputs unloaded.
4 Linearity is tested using a reduced code range: AD5337 (Code 8 to Code 248), AD5338, AD5338-1 (Code 28 to Code 995), AD5339 (Code 115 to Code 3981).
5 Guaranteed by design and characterization; not production tested.
6 For the amplifier output to reach its minimum voltage, offset error must be negative; to reach its maximum voltage, VREF = VDD and offset plus gain error must be positive.
7 IDD specification is valid for all DAC codes. Interface inactive. All DACs active and excluding load currents.


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