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74AUP1G34-Q100 Fiches technique(PDF) 9 Page - NXP Semiconductors |
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74AUP1G34-Q100 Fiches technique(HTML) 9 Page - NXP Semiconductors |
9 / 14 page 74AUP1G34_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet Rev. 1 — 26 March 2013 9 of 14 NXP Semiconductors 74AUP1G34-Q100 Low-power buffer [1] For measuring enable and disable times, RL = 5 k. For measuring propagation delays, setup and hold times and pulse width, RL =1M. Test data is given in Table 10. Definitions for test circuit: RL = Load resistance. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to the output impedance Zo of the pulse generator. VEXT = External voltage for measuring switching times. Fig 6. Test circuit for measuring switching times 001aac521 DUT RT VI VO VEXT VCC RL 5 k Ω CL G Table 10. Test data Supply voltage Load VEXT VCC CL RL [1] tPLH, tPHL tPZH, tPHZ tPZL, tPLZ 0.8 V to 3.6 V 5 pF, 10 pF, 15 pF and 30 pF 5 k or 1 M open GND 2 V CC |
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