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MM74C373 Fiches technique(PDF) 6 Page - Fairchild Semiconductor

No de pièce MM74C373
Description  3-STATE Octal D-Type Latch . 3-STATE Octal D-Type Flip-Flop
Download  11 Pages
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Fabricant  FAIRCHILD [Fairchild Semiconductor]
Site Internet  http://www.fairchildsemi.com
Logo FAIRCHILD - Fairchild Semiconductor

MM74C373 Fiches technique(HTML) 6 Page - Fairchild Semiconductor

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6
AC Electrical Characteristics (Note 7)
MM74C374, TA = 25°C, CL = 50 pF, tr = tf = 20 ns, unless otherwise noted
Note 7: AC Parameters are guaranteed by DC correlated testing.
Note 8: Capacitance is guaranteed by periodic testing.
Note 9: CPD determines the no load AC power consumption of any CMOS device. For complete explanation see Family Characteristics Application Note
AN-90.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
tpd0, tpd1
Propagation Delay,
VCC = 5V, CL = 50 pF
150
300
ns
CLOCK to Output
VCC = 10V, CL = 50 pF
65
130
VCC = 5V, CL = 150 pF
180
360
VCC = 10V, CL = 150 pF
80
160
tSET-UP
Minimum Set-Up Time Data In
tHOLD = 0 ns
to CLOCK/LATCH ENABLE
VCC = 5V
70
140
ns
VCC = 10V
35
70
tPWH, tPWL Minimum CLOCK Pulse Width
VCC = 5V
70
140
ns
VCC = 10V
50
100
fMAX
Maximum CLOCK Frequency
VCC = 5V
3.5
7.0
MHz
VCC = 10V
5
10
t1H, t0H
Propagation Delay OUTPUT
RL = 10k, CL = 50 pF
DISABLE to High Impedance
VCC = 5V
105
210
ns
State (from a Logic Level)
VCC = 10V
60
120
tH1, tH0
Propagation Delay OUTPUT
RL = 10k, CL = 50 pF
DISABLE to Logic Level
VCC = 5V
105
210
ns
(from High Impedance State)
VCC = 10V
45
90
tTHL, tTLH
Transition Time
VCC = 5V, CL = 50 pF
65
130
ns
VCC = 10V, CL = 50 pF
35
70
VCC = 5V, CL = 150 pF
110
220
VCC = 10V, CL = 150 pF
70
140
tr, tf
Maximum CLOCK Rise
VCC = 5V
15
>2000
µs
and Fall Time
VCC = 10V
5
>2000
CCLK
Input Capacitance
CLOCK Input (Note 8)
7.5
10
pF
COD
Input Capacitance
OUTPUT DISABLE
7.5
10
pF
Input (Note 8)
CIN
Input Capacitance
Any Other Input (Note 8)
5
7.5
pF
COUT
Output Capacitance
High Impedance
10
15
pF
State (Note 8)
CPD
Power Dissipation Capacitance
Per Package (Note 9)
250
pF


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