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HCPL-7850 Fiches technique(PDF) 6 Page - AVAGO TECHNOLOGIES LIMITED

No de pièce HCPL-7850
Description  Hermetically Sealed Analog Isolation Amplifi er
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Fabricant  AVAGO [AVAGO TECHNOLOGIES LIMITED]
Site Internet  http://www.avagotech.com
Logo AVAGO - AVAGO TECHNOLOGIES LIMITED

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6
AC Electrical Specifications
Over recommended operating conditions (TA = -55° C to +125° C, VIN+ = 0 V, VIN– = 0 V, VDD1 = 5 V and VDD2 = 5 V, unless
otherwise specified).
Parameter
Symbol
Group A[12]
Subgroups
Min.
Typ.*
Max.
Units
Test Conditions
Fig.
Note
Common Mode
Rejection
CMR
9
5
8
5.0
kV/
s
VCM = 1 kV
4.5 V ≤ (VDD1, VDD2)
≤ 5.5 V, TA = 25° C
16
8, 13
Propagation
Delay to 50%
tPD50
9, 10, 11
3.7
7.5
s
VIN+ = 0 to 100 mV step
4.5 V ≤ (VDD1, VDD2)
≤ 5.5 V
18, 19
Propagation
Delay to 90%
tPD90
9, 10, 11
5.7
11.0
Rise/Fall Time
(10-90%)
tR/F
9, 10, 11
3.4
7.5
Small-Signal
Bandwidth
(-3 dB)
f-3 dB
9, 10, 11
45
100
kHz
4.5 V ≤ (VDD1, VDD2)
≤ 5.5 V
VIN+ = 200 mVpk-pk
18, 20,
21
14
Small-Signal
Bandwidth
(-45°)
f-45°31
RMS Input-
Referred Noise
VN
0.6
mVrms
In recommended
application circuit
22, 24
9
Power Supply
Rejection
PSR
570
mVP-P
10
*
All typicals are at the nominal operating conditions of VIN+ = 0 V, VIN– = 0 V, TA = 25˚ C, VDD1 = 5 V and VDD2 = 5 V.
Notes:
1.
If VIN– is brought above VDD1 -2 V with respect to GND1 an internal test mode may be activated. This test mode is not intended for customer use.
2.
Exact offset value is dependent on layout of external bypass capacitors. The offset value in the data sheet corresponds to Avago’s recommended
layout (see Figures 26 and 27).
3.
Nonlinearity is defined as half of the peak-to-peak output deviation from the best-fit gain line, expressed as a percentage of the full-scale
differential output voltage.
4.
Because of the switched capacitor nature of the sigma-delta A/D converter, time averaged values are shown.
5.
CMRRIN is defined as the ratio of the gain for differential inputs applied between pins 2 and 3 to the gain for both common mode inputs applied
to both pins 2 and 3 with respect to pin 4.
6.
When the differential input signal exceeds approximately 320 mV, the outputs will limit at the typical values shown.
7.
Short-circuit current is the amount of output current generated when either output is shorted to VDD2 or ground. Avago does not recommend
operations under these conditions.
8.
CMR (also known as IMR or Isolation Mode Rejection) specifies the minimum rate of rise of a common mode signal applied across the isolation
boundary at which small output perturbations begin to occur. These output perturbations can occur with both the rising and falling edges of
the common mode waveform and may be of either polarity. A CMR failure is defined as a perturbation exceeding 200 mV at the output of the
recommended application circuit (Figure 24). See Applications section for more information on CMR.
9.
Output noise comes from two primary sources: chopper noise and sigma-delta quantization noise. Chopper noise results from chopper
stabilization of the output op-amps. It occurs at a specific frequency (typically 500 kHz) and is not attenuated by the on-chip output filter. The
on-chip filter does eliminate most, but not all, of the sigma-delta quantization noise. An external filter circuit may be easily added to the external
post-amplifier to reduce the total RMS output noise. See Applications section for more information.
10. Data sheet value is the amplitude of the transient at the differential output of the device when a 1 VP-P, 1 MHz square wave with 100 ns rise and
fall times (measured at pins 1 and 8) is applied to both VDD1 and VDD2.
11. Device considered a two-terminal device: Pins 1, 2, 3, and 4 are shorted together and pins 5, 6, 7, and 8 are shorted together.
12. Commercial parts receive 100% testing at 25° C (Subgroups 1 and 9). Hi-Rel and SMD parts receive 100% testing at 25° C, +125° C and -55° C
(Subgroups 1 and 9, 2 and 10, 3 and 11, respectively).
13. Parameters are tested as part of device initial characterization and after design and process changes only. Parameters are guaranteed to limits
specified for all lots not specifically tested.
14. The f-3dB test is guaranteed by the TRISE test.


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