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ADRF6702 Fiches technique(PDF) 2 Page - Analog Devices

No de pièce ADRF6702
Description  1200 MHz to 2400 MHz Quadrature Modulator
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Site Internet  http://www.analog.com
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ADRF6702
Data Sheet
Rev. B | Page 2 of 36
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Timing Characteristics ................................................................ 6
Absolute Maximum Ratings............................................................ 7
ESD Caution.................................................................................. 7
Pin Configuration and Function Descriptions............................. 8
Typical Performance Characteristics ........................................... 10
Theory of Operation ...................................................................... 16
PLL + VCO.................................................................................. 16
Basic Connections for Operation............................................. 16
External LO ................................................................................. 16
Loop Filter ................................................................................... 17
DAC-to-IQ Modulator Interfacing .......................................... 18
Adding a Swing-Limiting Resistor ........................................... 18
IQ Filtering .................................................................................. 19
Baseband Bandwidth ................................................................. 19
Device Programming and Register Sequencing..................... 19
Register Summary .......................................................................... 20
Register Description....................................................................... 21
Register 0—Integer Divide Control (Default: 0x0001C0) .... 21
Register 1—Modulus Divide Control (Default: 0x003001).. 22
Register 2—Fractional Divide Control (Default: 0x001802) 22
Register 3—Σ-Δ Modulator Dither Control (Default:
0x10000B).................................................................................... 23
Register 4—PLL Charge Pump, PFD, and Reference Path
Control (Default: 0x0AA7E4)................................................... 24
Register 5—LO Path and Modulator Control (Default:
0x0000D5) ................................................................................... 26
Register 6—VCO Control and VCO Enable (Default:
0x1E2106).................................................................................... 27
Register 7—External VCO Enable ........................................... 27
Characterization Setups................................................................. 28
Evaluation Board ............................................................................ 30
Evaluation Board Control Software......................................... 30
Outline Dimensions ....................................................................... 35
Ordering Guide .......................................................................... 35
REVISION HISTORY
10/11—Rev. A to Rev. B
Changes Table 1 ................................................................................ 1
7/11—Rev. 0 to Rev. A
Changes to Noise Floor in Features Section and Table 1 ............ 1
Changes to Specifications Section .................................................. 2
Changes to Figure 16, Figure 17, and Figure 18 ......................... 12
Changes to Figure 28...................................................................... 14
Changes to Figure 32 and Figure 34............................................. 15
Added Figure 34, Renumbered Sequentially .............................. 15
Changes to Figure 35...................................................................... 17
Added Figure 40.............................................................................. 19
Changes to Figure 52...................................................................... 31
4/11—Revision 0: Initial Version


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