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AD1981BJSTZ-REEL Fiches technique(PDF) 24 Page - Analog Devices |
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AD1981BJSTZ-REEL Fiches technique(HTML) 24 Page - Analog Devices |
24 / 32 page AD1981B Rev. C | Page 24 of 32 SPDIF CONTROL REGISTER Index 0x3A Reg No. Name D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Default 0x3A SPDIF Control V X SPSR1 SPSR0 L CC6 CC5 CC4 CC3 CC2 CC1 CC0 PRE COPY AUD PRO 0x2000 Register 0x3A is a read/write register that controls SPDIF functionality and manages bit fields propagated as channel status (or subframe in the V case). With the exception of V, this register should be written to only when the SPDIF transmitter is disabled (SPDIF bit in Register 0x2A is 0). This ensures that control and status information start up correctly at the beginning of SPDIF transmission. Table 35. Bit Mnemonic Function PRO Professional 1 = Professional use of channel status. 0 = Consumer. AUD Nonaudio 1 = Data is non-PCM format. 0 = Data is PCM format. COPY Copyright 1 = Copyright is asserted. 0 = Copyright is not asserted. PRE Pre-emphasis 1 = Filter pre-emphasis is 50 µs/15 µs. 0 = Pre-emphasis is none. CC [6:0] Category Code Programmed according to IEC standards, or as appropriate. L Generation Level Programmed according to IEC standards, or as appropriate. SPSR [1:0] SPDIF Transmit Sample Rate SPSR [1:0] = 00: Transmit sample rate is 44.1 kHz. SPSR [1:0] = 01: Reserved. SPSR [1:0] = 10: Transmit sample rate is 48 kHz (reset default). SPSR [1:0] = 11: Not supported. V Validity This bit affects the validity flag (Bit 28 transmitted in each SPDIF L/R subframe) and enables the SPDIF transmitter to maintain connection during error or mute conditions. V = 1: Each SPDIF subframe (L + R) has Bit 28 set to 1. This tags both samples as invalid. V = 0: Each SPDIF subframe (L + R) has Bit 28 set to 0 for valid data and 1 for invalid data (error condition). When V = 0, asserting the VFORCE bit (D15) in Register 0x2A (Ext’d Audio Stat/Ctrl) forces the validity flag low, marking both samples as valid. EQ CONTROL REGISTER Index 0x60 Reg No. Name D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Default 0x60 EQ Ctrl EQM MAD LBEN X X X X X X SYM CHS BCA5 BCA4 BCA3 BCA2 BCA1 BCA0 0x8080 Register 0x60 is a read/write register that controls the equalizer functionality and data setup. This register contains the biquad and coefficient address pointer, which is used in conjunction with the EQ data register (0x78) to set up the equalizer coefficients. The reset default disables the equalizer function until the coefficients can be properly set up by the software and sets the symmetry bit to allow equal coefficients for left and right channels. All registers are not shown, and bits containing an X are assumed to be reserved. Table 36. Bit Mnemonic Function BCA [5:0] Biquad and Coefficient Address Pointer biquad 0 coef a0 BCA[5:0] = 011011 biquad 0 coef a1 BCA[5:0] = 011010 biquad 0 coef a2 BCA[5:0] = 011001 biquad 0 coef b1 BCA[5:0] = 011101 biquad 0 coef b2 BCA[5:0] = 011100 biquad 1 coef a0 BCA[5:0] = 100000 biquad 1 coef a1 BCA[5:0] = 011111 |
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