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LM49370RLX-NOPB Fiches technique(PDF) 38 Page - Texas Instruments |
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LM49370RLX-NOPB Fiches technique(HTML) 38 Page - Texas Instruments |
38 / 89 page I2S CLKGEN ADC_CLOCK DAC_CLOCK I2S_CLK_IN I2S WSGEN I2S_WS_IN I2S_WS I2S_WS_OUT I2S_CLK I2S_CLK_OUT LM49370 SNAS356D – FEBRUARY 2007 – REVISED MARCH 2012 www.ti.com I2S PORT MODE CONFIGURATION REGISTER This register is used to control the audio data interfaces. Table 33. I2S Mode (0x1Ah) Bit Field Description s 0 I2S_OUT_ENB If set, the I2S output bus is enabled. If cleared, the I2S output will be tristate and all RX clocks will be gated. 1 I2S_IN_ENB If set, the I2S input is enabled. If this bit cleared, the I2S input is ignored and all TX clocks gated. 2 I2S_MODE This programs the format of the I2S interface. Definition 0 Normal 1 Left Justified 3 I2S_STEREO_REVERSE If set, the left and right channels are reversed. Operation 0 Normal 1 Reversed 4 I2S_WS_MS If set, I2S_WS generation is enabled and is Master. If cleared, I2S_WS acts as slave. 6:5 I2S_WS_GEN_MODE This programs the I2S word length. Bits/Word 002 16 012 25 102 32 112 — 7 I2S_WORD_ORDER This bit alters the RX phasing of left and right channels. If this bit is cleared: right then left. If this bit is set: left then right. Figure 18. I2S Audio Port CLOCK/SYNC Options I2S PORT CLOCK CONFIGURATION REGISTER This register is used to control the audio data interfaces. Table 34. I2S Clock (0x1Bh) Bit Field Description s 0 I2S_CLOCK_MS If set, then I2S clock generation is enabled and is Master. If this bit is cleared, then the I2S clock is driven by the device slave. 1 I2S_CLOCK_SOURCE This selects the source of the clock to be used by the I2S clock generator. I2S_CLOCK_SOURCE Clock is source from 0 DAC (from R divider) 1 ADC (from Q divider) 38 Submit Documentation Feedback Copyright © 2007–2012, Texas Instruments Incorporated Product Folder Links: LM49370 |
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