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AD9279 Fiches technique(PDF) 7 Page - Analog Devices

No de pièce AD9279
Description  Octal LNA/VGA/AAF/ADC and CW I/Q Demodulator
Download  44 Pages
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Fabricant  AD [Analog Devices]
Site Internet  http://www.analog.com
Logo AD - Analog Devices

AD9279 Fiches technique(HTML) 7 Page - Analog Devices

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AD9279
Rev. 0 | Page 7 of 44
SWITCHING SPECIFICATIONS
AVDD1 = 1.8 V, AVDD2 = 3.0 V, DRVDD = 1.8 V, full temperature, unless otherwise noted.
Table 3.
Parameter1
Temperature
Min
Typ
Max
Unit
CLOCK2
Clock Rate
40 MSPS (Mode I)
Full
18.5
40
MHz
65 MSPS (Mode II)
Full
18.5
65
MHz
80 MSPS (Mode III)
Full
18.5
80
MHz
Clock Pulse Width High (tEH)
Full
6.25
ns
Clock Pulse Width Low (tEL)
Full
6.25
ns
OUTPUT PARAMETERS2, 3
Propagation Delay (tPD)
Full
(tSAMPLE/2) + 1.5
(tSAMPLE/2) + 2.3
(tSAMPLE/2) + 3.1
ns
Rise Time (tR) (20% to 80%)
Full
300
ps
Fall Time (tF) (20% to 80%)
Full
300
ps
FCO Propagation Delay (tFCO)
Full
(tSAMPLE/2) + 1.5
(tSAMPLE/2) + 2.3
(tSAMPLE/2) + 3.1
ns
DCO Propagation Delay (tCPD)4
Full
tFCO + (tSAMPLE/24)
ns
DCO to Data Delay (tDATA)4
Full
(tSAMPLE/24) − 300
(tSAMPLE/24)
(tSAMPLE/24) + 300
ps
DCO to FCO Delay (tFRAME)4
Full
(tSAMPLE/24) − 300
(tSAMPLE/24)
(tSAMPLE/24) + 300
ps
Data-to-Data Skew (tDATA-MAX − tDATA-MIN)
Full
±100
±350
ps
Wake-Up Time (Standby), GAIN+ = 0.5 V
25°C
2
μs
Wake-Up Time (Power-Down)
25°C
1
ms
Pipeline Latency
Full
8
Clock
cycles
APERTURE
Aperture Uncertainty (Jitter)
25°C
<1
ps rms
LO GENERATION
4LO Frequency
Full
4
40
MHz
LO Divider RESET Setup Time5
Full
5
ns
LO Divider RESET Hold Time5
Full
5
ns
LO Divider RESET High Pulse Width
Full
20
ns
1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and information about how these tests were
completed.
2 Can be adjusted via the SPI.
3 Measurements were made using a part soldered to FR-4 material.
4 tSAMPLE/24 is based on the number of bits divided by 2 because the delays are based on half duty cycles.
5 RESET edge to rising 4LO edge.


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