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AD7938BSUZ-REEL7 Fiches technique(PDF) 9 Page - Analog Devices |
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AD7938BSUZ-REEL7 Fiches technique(HTML) 9 Page - Analog Devices |
9 / 36 page Data Sheet AD7938/AD7939 Rev. C | Page 9 of 36 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS PIN 1 INDICATOR 1 DB0 2 DB1 3 DB2 4 DB3 5 DB4 6 DB5 7 DB6 8 DB7 24 VIN1 23 VIN0 22 VREFIN/VREFOUT 21 AGND 20 CS 19 RD 18 WR 17 CONVST TOP VIEW (Not to Scale) AD7938/AD7939 NOTES 1. THE EXPOSED PAD IS LOCATED ON THE UNDERSIDE OF THE PACKAGE. CONNECT THE EPAD TO THE GROUND PLANE OF THE PCB USING MULTIPLE VIAS. Figure 2. LFCSP Pin Configuration 1 2 3 4 5 6 7 8 DB1 DB2 DB3 DB6 DB5 DB4 DB0 DB7 23 VIN0 22 VREFIN/VREFOUT 21 AGND 18 WR 19 RD 20 CS 24 VIN1 17 CONVST PIN 1 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 AD7938/AD7939 TOP VIEW (Not to Scale) Figure 3. TQFP Pin Configuration Table 6. Pin Function Descriptions Pin No. Mnemonic Description 1 to 8 DB0 to DB7 Data Bit 0 to Data Bit 7. Three-state parallel digital I/O pins that provide the conversion result and allow the control and shadow registers to be programmed. These pins are controlled by CS, RD, and WR. The logic high/low voltage levels for these pins are determined by the VDRIVE input. When reading from the AD7939, the two LSBs (DB0 and DB1) are always 0 and the LSB of the conversion result is available on DB2. 9 VDRIVE Logic Power Supply Input. The voltage supplied at this pin determines at what voltage the parallel interface of the AD7938/AD7939 operates. This pin should be decoupled to DGND. The voltage at this pin can be different to that at VDD but should never exceed VDD by more than 0.3 V. 10 DGND Digital Ground. This is the ground reference point for all digital circuitry on the AD7938/AD7939. This pin should connect to the DGND plane of a system. The DGND and AGND voltages should ideally be at the same potential and must not be more than 0.3 V apart, even on a transient basis. 11 DB8/HBEN Data Bit 8/High Byte Enable. When W/B is high, this pin acts as Data Bit 8, a three-state I/O pin that is controlled by CS, RD, and WR. When W/B is low, this pin acts as the high byte enable pin. When HBEN is low, the low byte of data being written to or read from the AD7938/AD7939 is on DB0 to DB7. When HBEN is high, the top four bits of the data being written to or read from the AD7938/AD7939 are on DB0 to DB3. When reading from the device, DB4 to DB6 of the high byte contains the ID of the channel to which the conversion result corresponds (see the channel address bits in Table 10). When writing to the device, DB4 to DB7 of the high byte must be all 0s. Note that when reading from the AD7939, the two LSBs of the low byte are 0s, and the remaining six bits are conversion data. 12 to 14 DB9 to DB11 Data Bit 9 to Data Bit 11. Three-state parallel digital I/O pins that provide the conversion result and allow the control and shadow registers to be programmed in word mode. These pins are controlled by CS, RD, and WR. The logic high/low voltage levels for these pins are determined by the VDRIVE input. 15 BUSY Busy Output. Logic output that indicates the status of the conversion. The BUSY output goes high following the falling edge of CONVST and stays high for the duration of the conversion. Once the conversion is complete and the result is available in the output register, the BUSY output goes low. The track-and-hold returns to track mode just prior to the falling edge of BUSY on the 13th rising edge of CLKIN. See Figure 36. 16 CLKIN Master Clock Input. The clock source for the conversion process is applied to this pin. Conversion time for the AD7938/AD7939 takes 13 clock cycles + t2. The frequency of the master clock input therefore determines the conversion time and achievable throughput rate. The CLKIN signal may be a continuous or burst clock. 17 CONVST Conversion Start Input. A falling edge on CONVST is used to initiate a conversion. The track-and-hold goes from track mode to hold mode on the falling edge of CONVST and the conversion process is initiated at this point. Following power-down, when operating in autoshutdown or autostandby modes, a rising edge on CONVST is used to power up the device. 18 WR Write Input. Active low logic input used in conjunction with CS to write data to the internal registers. 19 RD Read Input. Active low logic input used in conjunction with CS to access the conversion result. The conversion result is placed on the data bus following the falling edge of RD read while CS is low. 20 CS Chip Select. Active low logic input used in conjunction with RD and WR to read conversion data or to write data to the internal registers. |
Numéro de pièce similaire - AD7938BSUZ-REEL7 |
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Description similaire - AD7938BSUZ-REEL7 |
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