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74LVC1G175GW.125 Fiches technique(PDF) 8 Page - NXP Semiconductors |
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74LVC1G175GW.125 Fiches technique(HTML) 8 Page - NXP Semiconductors |
8 / 20 page 74LVC1G175 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 5 — 6 December 2011 8 of 20 NXP Semiconductors 74LVC1G175 Single D-type flip-flop with reset; positive-edge trigger [1] Typical values are measured at Tamb =25 C and VCC = 1.8 V, 2.5 V, 2.7 V, 3.3 V and 5.0 V respectively. [2] tpd is the same as tPLH and tPHL. [3] CPD is used to determine the dynamic power dissipation (PD in W). PD =CPD VCC2 fi N+ (CL VCC2 fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in Volts; N = number of inputs switching; (C L VCC 2 f o) = sum of the outputs. th hold time D to CP; see Figure 7 VCC = 1.65 V to 1.95 V 0.0 - - 0.0 - ns VCC = 2.3 V to 2.7 V 0.3 - - 0.3 - ns VCC = 2.7 V 0.5 - - 0.5 - ns VCC = 3.0 V to 3.6 V 1.2 0.2 - 1.2 - ns VCC = 4.5 V to 5.5 V 0.5 - - 0.5 - ns fmax maximum frequency CP; see Figure 7 VCC = 1.65 V to 1.95 V 80 125 - 80 - MHz VCC = 2.3 V to 2.7 V 175 - - 175 - MHz VCC = 2.7 V 175 - - 175 - MHz VCC = 3.0 V to 3.6 V 175 300 - 175 - MHz VCC = 4.5 V to 5.5 V 200 - - 200 - MHz CPD power dissipation capacitance VI = GND to VCC; VCC =3.3 V [3] -14 - - - pF Table 8. Dynamic characteristics …continued Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 9. Symbol Parameter Conditions 40 C to +85 C 40 C to +125 C Unit Min Typ[1] Max Min Max |
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