SI826X datasheet(6/42 Pages) SILICONIMAGE

No de pièce	SI826X

Description	5 KV LED EMULATOR INPUT, 4.0 A ISOLATED GATE DRIVERS

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Si826x

6

Preliminary Rev. 0.9

UVLO Threshold +

(Si826xxBx mode)

VDDUV+

See Figure 11 on page 17.

VDD rising

7.5

8.4

9.4

V

UVLO Threshold –

(Si826xxBx mode)

VDDUV–

See Figure 11 on page 17.

VDD falling

6.9

7.9

8.9

V

UVLO lockout hysteresis

(Si826xxBx mode)

VDDHYS

—500

—

mV

UVLO Threshold +

(Si826xxCx mode)

VDDUV+

See Figure 12 on page 17.

VDD rising

10.5

12

13.5

V

UVLO Threshold –

(Si826xxCx mode)

VDDUV–

See Figure 12 on page 17.

VDD falling

9.4

10.7

12.2

V

UVLO lockout hysteresis

(Si826xxCx mode)

VDDHYS

—1.3

—

V

AC Switching Parameters

Propagation delay (Low-to-High)

tPLH

CL = 200 pF

20

40

60

ns

Propagation delay (High-to-Low)

tPHL

CL = 200 pF

10

30

50

ns

Pulse Width Distortion

PWD

|tPLH –tPHL|—

10

—

ns

Propagation Delay Difference

PDD

|tPHLMAX –tPLHMIN|—

—

20

ns

Rise time

tR

CL = 200 pF

—

5.5

15

ns

Fall time

tF

CL = 200 pF

—

8.5

20

ns

Device Startup Time

tSTART

—16

30

µs

Common Mode

Transient Immunity

CMTI

Output = low or high

(VCM = 1500 V), (IF > 6mA)

(See Figure 3)

35

50

—

kV/µs

Table 2. Electrical Characteristics (Continued)1

VDD =15V or 30V, GND=0V, IF =6mA, TA = –40 to +125 °C; typical specs at 25 °C

Parameter

Symbol

Test Conditions

Min

Typ

Max

Units

Notes:

1. See "8.Ordering Guide" on page 25 for more information.

2. Minimum value of (VDD - GND) decoupling capacitor is 1 µF.

3. Both VO pins are required to be shorted together for 4.0 A compliance.

4. When performing this test, it is recommended that the DUT be soldered to avoid trace inductances, which may cause

over-stress conditions.

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