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74HCT259PW Fiches technique(PDF) 5 Page - NXP Semiconductors |
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74HCT259PW Fiches technique(HTML) 5 Page - NXP Semiconductors |
5 / 23 page 74HC_HCT259 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved. Product data sheet Rev. 5 — 7 August 2012 5 of 22 NXP Semiconductors 74HC259; 74HCT259 8-bit addressable latch [1] H = HIGH voltage level; L = LOW voltage level. 7. Limiting values [1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed. [2] Ptot derates linearly with 12 mW/K above 70 C. [3] Ptot derates linearly with 8 mW/K above 70 C. [4] Ptot derates linearly with 5.5 mW/K above 60 C. [5] Ptot derates linearly with 4.5 mW/K above 60 C. Table 4. Operating mode select table[1] LE MR Mode L H Addressable latch mode H H Memory mode L L Demultiplexer mode HL Reset mode Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Max Unit VCC supply voltage 0.5 +7.0 V IIK input clamping current VI < 0.5 V or VI >VCC +0.5 V [1] - 20 mA IOK output clamping current VO < 0.5 V or VO > VCC + 0.5 V [1] - 20 mA IO output current VO = 0.5 V to VCC +0.5 V - 25 mA ICC supply current - +70 mA IGND ground current 70 - mA Tstg storage temperature 65 +150 C Ptot total power dissipation Tamb = 40 C to +125 C DIP16 package [2] - 750 mW SO16 package [3] - 500 mW (T)SSOP16 package [4] - 500 mW DHVQFN16 package [5] - 500 mW |
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