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AD5429YRUZ-REEL7 Fiches technique(PDF) 6 Page - Analog Devices

No de pièce AD5429YRUZ-REEL7
Description  Dual 8-/10-/12-Bit, High Bandwidth, Multiplying DACs with Serial Interface
Download  32 Pages
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Fabricant  AD [Analog Devices]
Site Internet  http://www.analog.com
Logo AD - Analog Devices

AD5429YRUZ-REEL7 Fiches technique(HTML) 6 Page - Analog Devices

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AD5429/AD5439/AD5449
Rev. C | Page 6 of 32
t8
t7
t12
t1
t3
t2
t4
t5
t6
DB15
(N)
DB15
(N + 1)
DB0
(N)
DB0
(N + 1)
DB15
(N)
DB0
(N)
SCLK
SYNC
SDIN
SDO
NOTES
1. ALTERNATIVELY, DATA CAN BE CLOCKED INTO THE INPUT SHIFT REGISTER ON THE RISING EDGE OF SCLK AS
DETERMINED BY THE CONTROL BITS. IN THIS CASE, DATA WOULD BE CLOCKED OUT OF SDO ON THE FALLING
EDGE OF SCLK. TIMING IS AS ABOVE, WITH SCLK INVERTED.
Figure 3. Daisy-Chain Timing Diagram
SDO
SDIN
SYNC
SCLK
16
32
DB15
DB0
DB15
DB0
DB15
UNDEFINED
NOP CONDITION
DB0
INPUT WORD SPECIFIES
REGISTER TO BE READ
SELECTED REGISTER DATA
CLOCKED OUT
Figure 4. Readback Mode Timing Diagram
200
μAIOL
200
μAIOH
TO OUTPUT
PIN
CL
50pF
VOH (MIN) + VOL (MAX)
2
Figure 5. Load Circuit for SDO Timing Specifications


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