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FMS6410 Fiches technique(PDF) 3 Page - Fairchild Semiconductor

No de pièce FMS6410
Description  Dual Channel Video Drivers with Integrated Filters and Composite Video Summer
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Fabricant  FAIRCHILD [Fairchild Semiconductor]
Site Internet  http://www.fairchildsemi.com
Logo FAIRCHILD - Fairchild Semiconductor

FMS6410 Fiches technique(HTML) 3 Page - Fairchild Semiconductor

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FMS6410
REV. 0.0.2 9/3/02
3
Functional Description
Introduction
The FMS6410 is a dual monolithic continuous time video
filter designed for reconstructing the luminance and chromi-
nance signals from an S-Video D/A source. The Composite
video output is generated by summing the filtered Y and C
outputs. The chip is intended for use in applications with AC
coupled inputs and AC coupled outputs (See Figure 1). The
reconstruction filters approximate a 4th-order Butterworth
characteristic with an optimization toward low overshoot and
flat group delay. Y, C, and CV outputs are capable of driving
2VP-P into AC coupled 150
Ω video loads with up to 35pF of
load capacitance at the output pin. All channels are clamped
during sync to establish the appropriate output voltage swing
range. Thus the input coupling capacitors do not behave
according to the conventional RC time constant. Clamping
for all channels settles to less than 10mv within 5ms of a
change in video input sources. In most applications the input
coupling capacitors are 0.1µF. The Y and C inputs typically
sink 1µA during active video, which nominally tilts a
horizontal line by about 2mV at the Y output. During sync,
the clamp typically sources 20µA to restore the DC level.
The net result is that the average input current is zero.
Any change in the input coupling capacitor’s value will
inversely alter the amount of tilt per line. Such a change will
also linearly affect the clamp response times. This product is
robust and stable under all stated load and input conditions.
Capacitive bypassing of VCC directly to ground ensures this
performance.
Luminance (Y) I/O
The luma input is driven by either a low impedance source of
1VP-P or the output of a 75
Ω terminated line. The input is
required to be AC coupled via a 0.1µF coupling capacitor
which allows for a settling time of 5ms. The luma output is
capable of driving an AC coupled 150
Ω load at 2VP-P, or
1VP-P into a doubly terminated 75
Ω load. Up to 35pF of
load capacitance (at the output pin) can be driven without
stability or slew issues. The output is AC coupled with a
220µF or larger AC coupling capacitor.
Chrominance (C) I/O
The chroma input is driven by a low impedance source of
0.7VP-P or the output of a 75
Ω terminated line. The input is
required to be AC coupled via a 0.1µF coupling capacitor
which allows for a clamp setting time of 5ms. The chroma
output is capable of driving an AC coupled 150
Ω load at
2VP-P, or 1VP-P into a doubly terminated 75
Ω load. Up to
35pF of load capacitance can be driven without stability or
slew issues. A 0.1µF AC coupling capacitor is recommended
at the output. Since chrominance signals do not contain
low frequency components, the smaller 0.1µF cap is
recommended instead of the 220µF cap to reduce circuit
cost.
Composite Video (CV) Output
The composite video output is capable of driving 2 loads to
2VP-P. It is intended to drive a TV and a VCR. Either the TV
input or the VCR input can be shorted to ground and the
other output will still meet specifications. Up to 35pF of load
capacitance (at the output pin) can be driven without stability
or slew issues.
DC Coupled Output Applications
The 220µF capacitor coupled with the 150
Ω termination
forms a high pass filter that blocks the DC while passing the
video frequencies and avoiding tilt. Lower values such as
10µF would create a problem. By AC coupling, the average
DC level is zero. Thus, the output voltages of all channels
will be centered around zero. Alternately, DC coupling the
output of the FMS6410 is allowable. There are several
tradeoffs: The average DC level on the outputs will be 2V;
Each output will dissipate an additional 40mW nominally;
The application will need to accommodate a 1V DC offset
sync tip; And it is recommended to limit each output to one
150
Ω load.


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