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TPS73730DRBT Fiches technique(PDF) 6 Page - Texas Instruments |
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TPS73730DRBT Fiches technique(HTML) 6 Page - Texas Instruments |
6 / 31 page IN N/C EN 6 5 4 OUT NR/FB GND 1 2 3 1 2 3 4 5 IN OUT GND NR/FB EN TABISGND 6 IN N/C N/C EN 8 7 6 5 OUT N/C NR/FB GND 1 2 3 4 TPS737xx SBVS067O – JANUARY 2006 – REVISED JUNE 2012 www.ti.com PIN CONFIGURATIONS DCQ PACKAGE DRB PACKAGE SOT223-6 3mm x 3mm SON (TOP VIEW) (TOP VIEW) DRV PACKAGE(1) 2mm x 2mm SON (TOP VIEW) (1) Power dissipation may limit operating range. Check Thermal Information table. Table 1. Pin Descriptions SOT223 3×3 SON 2×2 SON PIN (DCQ) (DRB) (DRV) NAME PIN NO. PIN NO. PIN NO. DESCRIPTION IN 1 8 6 Unregulated input supply GND 3, 6 4, Pad 3, Pad Ground Driving the enable pin (EN) high turns on the regulator. Driving this pin low puts the regulator into shutdown mode. Refer to the Shutdown section under EN 5 5 4 Applications Information for more details. EN must not be left floating and can be connected to IN if not used. Fixed voltage versions only—connecting an external capacitor to this pin NR 4 3 2 bypasses noise generated by the internal bandgap, reducing output noise to very low levels. Adjustable voltage version only—this is the input to the control loop error FB 4 3 2 amplifier, and is used to set the output voltage of the device. OUT 2 1 1 Regulator output. A 1.0 μF or larger capacitor of any type is required for stability. NC — 2, 6, 7 5 Not connected 6 Submit Documentation Feedback Copyright © 2006–2012, Texas Instruments Incorporated |
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