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TPS5102IDBTR Fiches technique(PDF) 4 Page - Texas Instruments |
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TPS5102IDBTR Fiches technique(HTML) 4 Page - Texas Instruments |
4 / 34 page TPS5102 DUAL, HIGH-EFFICIENCY CONTROLLER FOR NOTEBOOK PC POWER SLVS239 - SEPTEMBER 1999 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 detailed description Vref (1.185 V) The reference voltage is used to set the output voltage and the overvoltage protection (COMP). Vref5 (5 V) The internal linear voltage regulator is used for the high-side driver bootstrap voltage. Since the input voltage range is from 4.5 V to 25 V, this feature offers a fixed voltage for the bootstrap voltage greatly simplifying the drive design. It is also used for powering the low side driver. The tolerance is 6%. 5-V Switch If the internal 5 V switch senses a 5-V input from REG5V_IN pin, the internal 5-V linear regulator will be disconnected from the MOSFET drivers. The external 5 V will be used for both the low-side driver and the high side bootstrap, thus increasing the efficiency. PWM/SKIP This pin is used to change between PWM and Skip mode. If the pin is lower than 0.5-V, the IC is in regular PWM mode; if a minimum 2-V is applied to this pin, the IC works in Skip mode. In light load condition (<0.2 A), the skip mode gives a short pulse to the low-side FET instead of a full pulse. By this control, switching frequency is lowered, reducing switching loss; also the output capacitor energy discharging through the output inductor and the low-side FET is prevented. Therefore, the IC can achieve high efficiency at light load conditions (< 0.2 A). err-amp Each channel has its own error amplifier to regulate the output voltage of the synchronous-buck converter. It is used in the PWM mode for the high output current condition (>0.2A). Voltage mode control is applied. skip comparator In Skip mode, each channel has its own hysteretic comparator to regulate the output voltage of the synchronous-buck converter. The hysteresis is set internally and typically at 8.5 mV. The delay from the comparator input to the driver output is typically 1.2 µs. low-side driver The low-side driver is designed to drive low-Rds(on) n-channel MOSFETs. The maximum drive voltage is 5 V from Vref5. The current rating of the driver is typically 1 A, source and sink. high-side driver The high side driver is designed to drive low-Rds(on) n-channel MOSFETs. The current rating of the driver is 1 A, source and sink. When configured as a floating driver, the bias voltage to the driver is developed from Vref5, limiting the maximum drive voltage between OUT_u and LL to 5 V. The maximum voltage that can be applied between LHx and OUTGND is 30 V. deadtime control Deadtime prevents shoot–through current from flowing through the main power FETs during switching transitions by actively controlling the turn-on time of the MOSFETs drivers. The typical deadtime from low-side-driver-off to high-side-driver-on is 70 ns, and 85 ns from high-side-driver-off to low-side-driver-on. |
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