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ADV7611BSWZ-P Fiches technique(PDF) 5 Page - Analog Devices |
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ADV7611BSWZ-P Fiches technique(HTML) 5 Page - Analog Devices |
5 / 16 page Data Sheet ADV7611 Rev. D | Page 5 of 16 DATA AND I2C TIMING CHARACTERISTICS Table 2. Parameter Symbol Test Conditions/Comments Min Typ Max Unit CLOCK AND CRYSTAL Crystal Frequency, XTALP 28.63636 MHz Crystal Frequency Stability ±50 ppm LLC Frequency Range1 13.5 165 MHz I2C PORTS SCL Frequency 400 kHz SCL Minimum Pulse Width High2 t1 600 ns SCL Minimum Pulse Width Low2 t2 1.3 μs Start Condition Hold Time2 t3 600 ns Start Condition Setup Time2 t4 600 ns SDA Setup Time2 t5 100 ns SCL and SDA Rise Time2 t6 300 ns SCL and SDA Fall Time2 t7 300 ns Stop Condition Setup Time2 t8 0.6 μs RESET FEATURE Reset Pulse Width 5 ms CLOCK OUTPUTS LLC Mark-Space Ratio2 t9:t10 45:55 55:45 % duty cycle DATA AND CONTROL OUTPUTS3 Data Output Transition Time2, 4 t11 End of valid data to negative clock edge 1.0 2.2 ns t12 Negative clock edge to start of valid data 0.0 0.3 ns I2S PORT, MASTER MODE SCLK Mark-Space Ratio2 t15:t16 45:55 55:45 % duty cycle LRCLK Data Transition Time2 t17 End of valid data to negative SCLK edge 10 ns LRCLK Data Transition Time2 t18 Negative SCLK edge to start of valid data 10 ns I2S Data Transition Time2, 5 t19 End of valid data to negative SCLK edge 5 ns I2S Data Transition Time2, 5 t20 Negative SCLK edge to start of valid data 5 ns 1 Maximum LLC frequency is limited by the clock frequency of UXGA 60 Hz at 8 bit. 2 Data guaranteed by characterization. 3 With the DLL block on output clock bypassed. 4 DLL bypassed on clock path. 5 I2S is accessible via the AP pin. |
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Description similaire - ADV7611BSWZ-P |
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