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AD7822BRUZ-REEL1 Fiches technique(PDF) 7 Page - Analog Devices |
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AD7822BRUZ-REEL1 Fiches technique(HTML) 7 Page - Analog Devices |
7 / 28 page AD7822/AD7825/AD7829 Rev. C | Page 7 of 28 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS DB2 1 DB1 2 DB0 3 CONVST 4 DB3 20 DB4 19 DB5 18 DB6 17 CS 5 RD 6 DGND 7 DB7 16 AGND 15 VDD 14 EOC 8 VREF IN/OUT 13 PD 9 VMID 12 NC 10 VIN1 11 NC = NO CONNECT AD7822 TOP VIEW (Not to Scale) DB2 1 DB1 2 DB0 3 CONVST 4 DB3 24 DB4 23 DB5 22 DB6 21 CS 5 DB7 20 RD 6 AGND 19 DGND 7 VDD 18 EOC 8 VREF IN/OUT 17 A1 9 VMID 16 A0 10 VIN1 15 PD 11 VIN2 14 VIN4 12 VIN3 13 AD7825 TOP VIEW (Not to Scale) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 DB1 DB0 CONVST DGND RD CS DB2 DB4 DB5 DB6 VDD AGND DB7 EOC A2 A1 VIN6 VIN8 A0 VREF IN/OUT VMID VIN1 VIN5 VIN7 VIN4 VIN3 VIN2 DB3 AD7829 TOP VIEW (Not to Scale) Figure 3. Pin Configuration Figure 4. Pin Configuration Figure 5. Pin Configuration Table 4. Pin Function Descriptions Mnemonic Description VIN1 to VIN8 Analog Input Channels. The AD7822 has a single input channel; the AD7825 and AD7829 have four and eight analog input channels, respectively. The inputs have an input span of 2.5 V and 2 V depending on the supply voltage (VDD). This span can be centered anywhere in the range AGND to VDD using the VMID pin. The default input range (VMID unconnected) is AGND to 2 V (VDD = 3 V ± 10%) or AGND to 2.5 V (VDD = 5 V ± 10%). See the Analog Input section of the data sheet for more information. VDD Positive Supply Voltage, 3 V ± 10% and 5 V ± 10%. AGND Analog Ground. Ground reference for track-and-hold, comparators, reference circuit, and multiplexer. DGND Digital Ground. Ground reference for digital circuitry. CONVST Logic Input Signal. The convert start signal initiates an 8-bit analog-to-digital conversion on the falling edge of this signal. The falling edge of this signal places the track-and-hold in hold mode. The track-and-hold goes into track mode again 120 ns after the start of a conversion. The state of the CONVST signal is checked at the end of a conversion. If it is logic low, the AD7822/ AD7825/AD7829 powers down (see the Operating Modes section of the data sheet). EOC Logic Output. The end-of-conversion signal indicates when a conversion has finished. The signal can be used to interrupt a microcontroller when a conversion has finished or latch data into a gate array (see the Parallel Interface section). CS Logic Input Signal. The chip select signal is used to enable the parallel port of the AD7822/AD7825/AD7829. This is necessary if the ADC is sharing a common data bus with another device. PD Logic Input. The power-down pin is present on the AD7822 and AD7825 only. Bringing the PD pin low places the AD7822 and AD7825 in power-down mode. The ADCs power up when PD is brought logic high again. RD Logic Input Signal. The read signal is used to take the output buffers out of their high impedance state and drive data onto the data bus. The signal is internally gated with the CS signal. Both RD and CS must be logic low to enable the data bus. A0 to A2 Channel Address Inputs. The address of the next multiplexer channel must be present on these inputs when the RD signal goes low. DB0 to DB7 Data Output Lines. They are normally held in a high impedance state. Data is driven onto the data bus when both RD and CS go active low. VREF IN/OUT Analog Input and Output. An external reference can be connected to the AD7822/AD7825/AD7829 at this pin. The on-chip reference is also available at this pin. When using the internal reference, this pin can be left unconnected or, in some cases, it can be decoupled to AGND with a 0.1 μF capacitor. VMID The VMID pin, if connected, is used to center the analog input span anywhere in the range of AGND to VDD (see the Analog Input section). |
Numéro de pièce similaire - AD7822BRUZ-REEL1 |
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Description similaire - AD7822BRUZ-REEL1 |
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