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AD7706BRU Datasheet(Fiches technique) 25 Page - Analog Devices

Numéro de pièce AD7706BRU
Description  3 V/5 V, 1 mW, 2-/3-Channel, 16-Bit, Sigma-Delta ADCs
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AD7706BRU Datasheet(HTML) 25 Page - Analog Devices

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Rev. C | Page 25 of 44
The digital filter does not provide any rejection at integer multiples
of the modulator sample frequency, as outlined earlier. However,
due to the part’s high oversampling ratio, these bands occupy
only a small fraction of the spectrum, and most broadband
noise is filtered. Therefore, the analog filtering requirements in
front of the AD7705/AD7706 are considerably reduced vs. a
conventional converter without on-chip filtering. In addition,
because the parts’ common-mode rejection performance of
100 dB extends to several kHz, common-mode noise in this
frequency range is substantially reduced.
Depending on the application, however, it might be necessary to
provide attenuation of the signal before it reaches the AD7705/
AD7706 to eliminate unwanted frequencies that can pass through
the digital filter. It might also be necessary to provide analog
filtering in front of the AD7705/AD7706 to ensure that differential
noise signals outside the band of interest do not saturate the
analog modulator.
If passive components are placed in front of the AD7705/
AD7706 in unbuffered mode, care must be taken to ensure that
the source impedance is low enough not to introduce gain errors
in the system. This significantly limits the amount of passive
antialiasing filtering, which can be provided in front of the
AD7705/AD7706 when the parts are used in unbuffered mode.
However, when the parts are used in buffered mode, large source
impedances result in a small dc offset error (a 10 kΩ source
resistance causes an offset error of less than 10 μV). Therefore,
if the system requires significant source impedances to provide
passive analog filtering in front of the AD7705/AD7706, it is
recommended to operate the part in buffered mode.
The AD7705/AD7706 provide a number of calibration options
that can be programmed via the MD1 and MD0 bits of the setup
register. The different calibration options are outlined in the
Setup Register (RS2, RS1, RS0 = 0, 0, 1); Power-On/Reset Status:
01 Hex, and Calibration Sequences sections. A calibration cycle
can be initiated at any time by writing to these bits of the setup
register. Calibration on the AD7705/AD7706 removes offset
and gain errors from the devices. A calibration routine should
be initiated on these devices whenever there is a change in the
ambient operating temperature or supply voltage. It should also
be initiated if there is a change in the selected gain, filter notch,
or bipolar/unipolar input range.
The AD7705/AD7706 offer self-calibration and system calibration
facilities. For full calibration to occur on the selected channel,
the on-chip microcontroller must record the modulator output
for two input conditions: zero-scale point and full-scale point.
These points are derived by performing a conversion on the
different input voltages provided to the input of the modulator
during calibration. As a result, the accuracy of the calibration is
only as good as the noise level that it provides in normal mode.
The result of the zero-scale calibration conversion is stored in
the zero-scale calibration register, and the result of the full-scale
calibration conversion is stored in the full-scale calibration register.
With these readings, the microcontroller can calculate the offset
and the gain slope for the input-to-output transfer function of
the converter. Internally, the part works with a resolution of
33 bits to determine the conversion result of 16 bits.
A self-calibration is initiated on the AD7705/AD7706 by writing
the appropriate values (0, 1) to the MD1 and MD0 bits of the
setup register. In self-calibration mode with a unipolar input
range, the zero-scale point used to determine the calibration
coefficients is with the inputs of the differential pair internally
shorted on the part (i.e., AIN(+) = AIN(−) = internal bias voltage
on the AD7705, and AIN = COMMON = internal bias voltage
on the AD7706). The PGA is set for the selected gain for this
zero-scale calibration conversion, as per the G1 and G0 bits in
the communication register. The full-scale calibration conversion
is performed at the selected gain on an internally generated
voltage of VREF/selected gain.
The duration time for the calibration is 6 × 1/output rate. This
is composed of 3 × 1/output rate for the zero-scale calibration
and 3 × 1/output rate for the full-scale calibration. Then, the
MD1 and MD0 bits in the setup register return to 0, 0. This
provides the earliest indication that the calibration sequence is
complete. The DRDY line goes high when calibration is initiated
and does not return low until there is a valid new word in the data
register. The duration time from the calibration command being
issued to DRDY going low is 9 × 1/output rate. This is composed
of 3 × 1/output rate for the zero-scale calibration, 3 × 1/output
rate for the full-scale calibration, 3 × 1/output rate for a conversion
on the analog input, and some overhead to set up the coeffi-
cients correctly. If DRDY is low before (or goes low during)
writing the calibration command to the setup register, it can
take up to one modulator cycle (MCLK IN/128) before DRDY
goes high to indicate that a calibration is in progress. Therefore,
DRDY should be ignored for one modulator cycle after the last
bit is written to the setup register in the calibration command.
For bipolar input ranges in the self-calibrating mode, the
sequence is very similar to that outlined in the previous
paragraph. In this case, the two points are the same as above,
but the shorted inputs point is midscale of the transfer function
because the part is configured for bipolar operation.
System Calibration
System calibration allows the AD7705/AD7706 to compensate
for system gain and offset errors, as well as their own internal
errors. System calibration performs the same slope factor
calculations as self-calibration, but uses voltage values presented
by the system to the AIN inputs for the zero- and full-scale points.
Full system calibration requires a two-step process, a zero-scale
system calibration followed by a full-scale system calibration.

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