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TC74A2-3.3VCTTR Datasheet(Fiches technique) 6 Page - Microchip Technology
Numéro de pièce
MICROCHIP [Microchip Technology]
TC74A2-3.3VCTTR Datasheet(HTML) 6 Page - Microchip Technology
/ 18 page
2001-2012 Microchip Technology Inc.
information from its onboard solid-state sensor with a
resolution of ±1°C. It stores the data in an internal
register which is then read through the serial port. The
system interface is a slave SMBus/I
C port, through
which temperature data can be read at any time. Eight
C addresses are programmable for the TC74,
which allows for a multi-sensor configuration. Also,
there is low power Standby mode when temperature
acquisition is suspended.
The host is allowed, by the TC74, to put it into a low
= 5 µA, typical) Standby mode. In this mode,
the A/D converter is halted and the temperature data
registers are frozen. The SMBus/I
C port, though,
operates normally. Standby mode is enabled by setting
the SHDN bit in the CONFIG register. Table 3-1
summarizes this operation.
STANDBY MODE OPERATION
C SLAVE ADDRESS
The TC74 is internally programmed to have a default
C address value of 1001 101b. Seven other
addresses are available by custom order (contact
Microchip Technology Inc.
Serial Port Operation
The Serial Clock input (SCLK) and bidirectional data
port (SDA) form a 2-wire bidirectional serial port for pro-
conventions used in this bus architecture are listed in
SERIAL BUS CONVENTIONS
All transfers take place under the control of a host, usu-
ally a CPU or microcontroller, acting as the Master. This
host provides the clock signal for all transfers. The
TC74 always operates as a Slave. The serial protocol
is illustrated in Figure 3-1. All data transfers have two
phases and all bytes are transferred MSB first.
Accesses are initiated by a START condition, followed
by a device address byte and one or more data bytes.
The device address byte includes a Read/Write selec-
tion bit. Each access must be terminated by a STOP
condition. A convention called “Acknowledge” (ACK)
confirms receipt of each byte. Note that SDA can
change only during periods when SCLK is low (SDA
changes while SCLK is high are reserved for START
and STOP conditions).
The device sending data to the bus.
The device receiving data from the bus.
The device which controls the bus initi-
ating transfers (START), generating the
clock and terminating transfers
The device addressed by the master.
A unique condition signaling the begin-
ning of a transfer indicated by SDA
falling (high-low) while SCLK is high.
A unique condition signaling the end of
a transfer indicated by SDA rising (low-
high) while SCLK is high.
A Receiver acknowledges the receipt
of each byte with this unique condition.
The Receiver drives SDA low during
SCLK high of the ACK clock-pulse. The
Master provides the clock pulse for the
Communication is not possible
because the bus is in use.
When the bus is idle, both SDA and
SCLK will remain high.
The state of SDA must remain stable
during the high period of SCLK in order
for a data bit to be considered valid.
SDA only changes state while SCLK is
low during normal data transfers (see
START and STOP conditions).
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