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FDN358 Fiches technique(PDF) 1 Page - Fairchild Semiconductor |
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FDN358 Fiches technique(HTML) 1 Page - Fairchild Semiconductor |
1 / 4 page March 1998 FDN358P P-Channel Logic Level Enhancement Mode Field Effect Transistor General Description Features Absolute Maximum Ratings T A = 25 oC unless other wise noted Symbol Parameter FDN358P Units V DSS Drain-Source Voltage -30 V V GSS Gate-Source Voltage ±20 V I D Drain/Output Current - Continuous -1.5 A - Pulsed -5 P D Maximum Power Dissipation (Note 1a) 0.5 W (Note 1b) 0.46 T J,TSTG Operating and Storage Temperature Range -55 to 150 °C THERMAL CHARACTERISTICS RθJA Thermal Resistance, Junction-to-Ambient (Note 1a) 250 °C/W RθJC Thermal Resistance, Junction-to-Case (Note 1) 75 °C/W FDN358P Rev.D -1.5 A, -30 V, R DS(ON) = 0.125 Ω @ VGS = -10 V R DS(ON) = 0.20 Ω @ VGS = - 4.5 V. High power version of industry SOT-23 package: identical pin out to SOT-23; 30% higher power handling capability. High density cell design for extremely low R DS(ON). Exceptional on-resistance and maximum DC current capability. SuperSOT TM-3 P-Channel logic level enhancement mode power field effect transistors are produced using Fairchild's proprietary, high cell density, DMOS technology. This very high density process is especially tailored to minimize on-state resistance. These devices are particularly suited for low voltage applications in notebook computers, portable phones, PCMCIA cards, and other battery powered circuits where fast switching, and low in-line power loss are needed in a very small outline surface mount package. G D S SuperSOT -3 TM 358 SuperSOT TM-8 SOIC-16 SO-8 SOT-223 SuperSOT TM-3 SuperSOT TM-6 D S G © 1998 Fairchild Semiconductor Corporation |
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