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FDN357N Fiches technique(PDF) 2 Page - Fairchild Semiconductor

No de pièce FDN357N
Description  N-Channel Logic Level Enhancement Mode Field Effect Transistor
Download  4 Pages
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Fabricant  FAIRCHILD [Fairchild Semiconductor]
Site Internet  http://www.fairchildsemi.com
Logo FAIRCHILD - Fairchild Semiconductor

FDN357N Fiches technique(HTML) 2 Page - Fairchild Semiconductor

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Electrical Characteristics (T
A = 25
O
C unless otherwise noted )
Symbol
Parameter
Conditions
Min
Typ
Max
Units
OFF CHARACTERISTICS
BV
DSS
Drain-Source Breakdown Voltage
V
GS = 0 V, ID = 250 µA
30
V
BV
DSS/TJ
Breakdown Voltage Temp. Coefficient
I
D = 250 µA, Referenced to 25
oC
36
mV/
oC
I
DSS
Zero Gate Voltage Drain Current
V
DS = 24 V, VGS = 0 V
1
µA
T
J = 55°C
10
µA
I
GSSF
Gate - Body Leakage, Forward
V
GS = 20 V,VDS = 0 V
100
nA
I
GSSR
Gate - Body Leakage, Reverse
V
GS = -20 V, VDS = 0 V
-100
nA
ON CHARACTERISTICS (Note)
V
GS(th)
Gate Threshold Voltage
V
DS = VGS, ID = 250 µA
1
1.6
2
V
V
GS(th)/TJ
Gate Threshold Voltage Temp. Coefficient
I
D = 250 µA, Referenced to 25
oC
-3.6
mV/
oC
R
DS(ON)
Static Drain-Source On-Resistance
V
GS = 4.5 V, ID = 1.9 A
0.081
0.09
T
J =125°C
0.11
0.14
V
GS = 10 V, ID = 2.2 A
0.053
0.06
I
D(ON)
On-State Drain Current
V
GS = 4.5 V, VDS = 5 V
5
A
g
FS
Forward Transconductance
V
DS = 5 V, ID = 1.9 A
5
S
DYNAMIC CHARACTERISTICS
C
iss
Input Capacitance
V
DS = 10 V, VGS = 0 V,
f = 1.0 MHz
235
pF
C
oss
Output Capacitance
145
pF
C
rss
Reverse Transfer Capacitance
50
pF
SWITCHING CHARACTERISTICS (Note)
t
D(on)
Turn - On Delay Time
V
DD = 10 V, ID = 1 A,
V
GS = 10 V, RGEN = 6
5
10
ns
t
r
Turn - On Rise Time
12
22
ns
t
D(off)
Turn - Off Delay Time
12
22
ns
t
f
Turn - Off Fall Time
3
8
ns
Q
g
Total Gate Charge
V
DS = 10 V, ID = 1.9 A,
V
GS = 5 V
4.2
5.9
nC
Q
gs
Gate-Source Charge
1.3
nC
Q
gd
Gate-Drain Charge
1.7
nC
DRAIN-SOURCE DIODE CHARACTERISTICS AND MAXIMUM RATINGS
I
S
Maximum Continuous Drain-Source Diode Forward Current
0.42
A
V
SD
Drain-Source Diode Forward Voltage
V
GS = 0 V, IS = 0.42 A (Note)
0.71
1.2
V
Note:
1. RθJA is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. RθJC is guaranteed by
design while RθCA is determined by the user's board design.
Typical RθJA using the board layouts shown below on 4.5"x5" FR-4 PCB in a still air environment :
Scale 1 : 1 on letter size paper
2. Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0%.
FDN357N Rev.C
a. 250
oC/W when mounted on
a 0.02 in
2 pad of 2oz Cu.
b. 270
oC/W when mounted on
a 0.001 in
2 pad of 2oz Cu.


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