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FDN338 Fiches technique(PDF) 1 Page - Fairchild Semiconductor

No de pièce FDN338
Description  P-Channel Logic Level Enhancement Mode Field Effect Transistor
Download  4 Pages
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Fabricant  FAIRCHILD [Fairchild Semiconductor]
Site Internet  http://www.fairchildsemi.com
Logo FAIRCHILD - Fairchild Semiconductor

FDN338 Fiches technique(HTML) 1 Page - Fairchild Semiconductor

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March 1998
FDN338P
P-Channel Logic Level Enhancement Mode Field Effect Transistor
General Description
Features
Absolute Maximum Ratings T
A = 25
oC unless other wise noted
Symbol
Parameter
FDN338P
Units
V
DSS
Drain-Source Voltage
-20
V
V
GSS
Gate-Source Voltage - Continuous
±8
V
I
D
Drain/Output Current - Continuous
-1.6
A
- Pulsed
-5
P
D
Maximum Power Dissipation
(Note 1a)
0.5
W
(Note 1b)
0.46
T
J,TSTG
Operating and Storage Temperature Range
-55 to 150
°C
THERMAL CHARACTERISTICS
RθJA
Thermal Resistance, Junction-to-Ambient (Note 1a)
250
°C/W
RθJC
Thermal Resistance, Junction-to-Case
(Note 1)
75
°C/W
FDN338P Rev.D
-1.6 A, -20 V, R
DS(ON) = 0.13 @ VGS = -4.5 V
R
DS(ON) = 0.18 @ VGS = -2.5 V.
Industry standard outline SOT-23 surface mount
package using proprietary SuperSOT
TM-3 design for
superior thermal and electrical capabilities.
High density cell design for extremely low R
DS(ON).
Exceptional on-resistance and maximum DC current
capability.
SuperSOT
TM-3 P-Channel logic level enhancement mode
power field effect transistors are produced using Fairchild's
proprietary, high cell density, DMOS technology. This very
high density process is especially tailored to minimize
on-state resistance. These devices are particularly suited for
low voltage applications in notebook computers, portable
phones, PCMCIA cards, and other battery powered circuits
where fast switching, and low in-line power loss are needed
in a very small outline surface mount package.
SuperSOT
TM-8
SOIC-16
SO-8
SOT-223
SuperSOT
TM-3
G
D
S
SuperSOT -3
TM
338
D
S
G
SuperSOT
TM-6
© 1998 Fairchild Semiconductor Corporation


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