ADF4108S

ASD0016548 Rev. A | Page 2 of 21

4.0.

Specifications

4.1. Absolute maximum ratings 1/

AVdd to GND ................................................................................................................................-0.3V to +3.9 V

AVdd to DVdd................................................................................................................................-0.3V to +0.3 V

Vp to GND ....................................................................................................................................-0.3V to +5.8 V

Vp to AVdd....................................................................................................................................-0.3V to +5.8 V

Digital I/O Voltage to GND ...................................................................................................-0.3V to Vdd + 0.3 V

Analog I/O Voltage to GND .....................................................................................................-0.3V to Vp +0.3 V

REFin, RFinA, RFinB to GND ...............................................................................................-0.3V to Vdd +0.3 V

RFinA to RFinB ………………………................................................................................................. +/- 600 mV

Operating Temperature Range ................................................................................................-55 ºC to +125 ºC

Storage Temperature Range................................................................................................... –65°C to +150 °C

Lead Temperature (Soldering 60 Sec).....................................................................................................+300 °C

Thermal resistance, junction-to-case (

θ

Thermal resistance, junction-to-ambient (

θ

4.2. Recommended operating conditions

AVdd = DVdd ………………………................................................................................................3.2 V to 3.6 V

Vp ………………………....................................................................................................................Vdd to 5.5 V

Ambient Operating Temperature Range …………….............................................................. -55 ºC to +125 ºC

RF Frequency....................................................................................................................... 1.0 GHz to 7.0 GHz

REF Frequency.................................................................................................................... 20 MHz to 250 MHz

Phase Detector

Max sampling Frequency ………………………................................................................................. 104 MHz

Logic In

Max Input Capacitance ……………………….......................................................................................... 10 pF

REFin

Max Input Capacitance ……………………….......................................................................................... 10 pF

Noise Characteristics

Normalized 1/f Noise (PN1_f) ................................................................................................. -122 dBc/Hz 4/

Phase Noise Performance 7900 MHz Output.......................................................................... -81 dBc/Hz 5/

Spurious Signals 7900 MHz Output.............................................................................................. -82 dBc 5/

NOTES

1/ Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional

operation of the device at these or any other conditions outside of those indicated in the operation sections of this specification is not implied. Exposure

to absolute maximum ratings for extended periods may affect device reliability.

2/ Measurement taken under absolute worst case condition and represents data taken with a thermal camera for highest power density location. See

MIL-STD-1835 for average package Theta JC numbers.

3/ PLL loop B/W = 500 kHz, measured at 100 kHz offset. The synthesizers phase noise is estimated by measuring the in-band phase noise at the

4/ 10 kHz offset; normalized to 1 GHz. The PLL phase noise is composed of 1/f (flicker) noise plus the normalized PLL noise floor. The formula for

calculating the 1/f noise contribution at an RF frequency,

5/ At VCO output and 1 kHz offset.

dB RF Amp so that the PLL RFin = +5dBm.