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ADF4108S Fiches technique(PDF) 2 Page - Analog Devices |
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ADF4108S Fiches technique(HTML) 2 Page - Analog Devices |
2 / 21 page ADF4108S ASD0016548 Rev. A | Page 2 of 21 4.0. Specifications 4.1. Absolute maximum ratings 1/ AVdd to GND ................................................................................................................................-0.3V to +3.9 V AVdd to DVdd................................................................................................................................-0.3V to +0.3 V Vp to GND ....................................................................................................................................-0.3V to +5.8 V Vp to AVdd....................................................................................................................................-0.3V to +5.8 V Digital I/O Voltage to GND ...................................................................................................-0.3V to Vdd + 0.3 V Analog I/O Voltage to GND .....................................................................................................-0.3V to Vp +0.3 V REFin, RFinA, RFinB to GND ...............................................................................................-0.3V to Vdd +0.3 V RFinA to RFinB ………………………................................................................................................. +/- 600 mV Operating Temperature Range ................................................................................................-55 ºC to +125 ºC Storage Temperature Range................................................................................................... –65°C to +150 °C Maximum Junction Temperature (TJ)........................................................................................................150 °C Lead Temperature (Soldering 60 Sec).....................................................................................................+300 °C Thermal resistance, junction-to-case ( θ JC)...........................................................................................31 °C/W 2/ Thermal resistance, junction-to-ambient ( θ JA)....................................................................................36 °C/W 2/ 4.2. Recommended operating conditions AVdd = DVdd ………………………................................................................................................3.2 V to 3.6 V Vp ………………………....................................................................................................................Vdd to 5.5 V Ambient Operating Temperature Range …………….............................................................. -55 ºC to +125 ºC 4.3. Nominal operating performance characteristics (TA = 25°C, AVDD = DVDD = 3.3V, GND = AGND = DGND = CPGND = 0V, VCP = 5V, RSET = 5.1kΩ, RFinB cap coupled to ground, unless otherwise noted) RF Frequency....................................................................................................................... 1.0 GHz to 7.0 GHz REF Frequency.................................................................................................................... 20 MHz to 250 MHz Phase Detector Max sampling Frequency ………………………................................................................................. 104 MHz Logic In Max Input Capacitance ……………………….......................................................................................... 10 pF REFin Max Input Capacitance ……………………….......................................................................................... 10 pF Noise Characteristics Normalized Phase Noise Floor (PNSYNTH)............................................................................... -223 dBc/Hz 3/ Normalized 1/f Noise (PN1_f) ................................................................................................. -122 dBc/Hz 4/ Phase Noise Performance 7900 MHz Output.......................................................................... -81 dBc/Hz 5/ Spurious Signals 7900 MHz Output.............................................................................................. -82 dBc 5/ NOTES 1/ Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions outside of those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum ratings for extended periods may affect device reliability. 2/ Measurement taken under absolute worst case condition and represents data taken with a thermal camera for highest power density location. See MIL-STD-1835 for average package Theta JC numbers. 3/ PLL loop B/W = 500 kHz, measured at 100 kHz offset. The synthesizers phase noise is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20 log N (where N is the N divider value) and 10log FPFD. So PNSYNTH = PNTOT – 10 log FPFD - 20 log N. 4/ 10 kHz offset; normalized to 1 GHz. The PLL phase noise is composed of 1/f (flicker) noise plus the normalized PLL noise floor. The formula for calculating the 1/f noise contribution at an RF frequency, fRF and at a frequency offset, f, is given by PN = PN1_f + 10 log(10 kHz/f) – 10log(fRF/ 1GHz). 5/ At VCO output and 1 kHz offset. fREFIN = 10MHz, fPFD = 1MHz, fRF = 7900MHz, N = 7900; Loop B/W = 30kHZ, VCO = ZComm CRO8000Z with +10 dB RF Amp so that the PLL RFin = +5dBm. |
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