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ISLA214P50 Fiches technique(PDF) 11 Page - Intersil Corporation

No de pièce ISLA214P50
Description  14-Bit, 500MSPS ADC
Download  39 Pages
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Fabricant  INTERSIL [Intersil Corporation]
Site Internet  http://www.intersil.com/cda/home
Logo INTERSIL - Intersil Corporation

ISLA214P50 Fiches technique(HTML) 11 Page - Intersil Corporation

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ISLA214P50
11
FN7571.2
December 10, 2012
CLKDIVRSTP Input Pull-down Resistance
RIpd
100
k
Ω
CLKDIVRSTN Input Pull-up Resistance
RIpu
100
k
Ω
LVDS OUTPUTS
Differential Output Voltage (Note 10)
VT
3mA Mode
612
mVP-P
Output Offset Voltage
VOS
3mA Mode
1120
1150
1200
mV
Output Rise Time
tR
240
ps
Output Fall Time
tF
240
ps
CMOS OUTPUTS
Voltage Output High
VOH
IOH = -500µA
OVDD - 0.3 OVDD - 0.1
V
Voltage Output Low
VOL
IOL = 1mA
0.1
0.3
V
Output Rise Time
tR
1.8
ns
Output Fall Time
tF
1.4
ns
NOTES:
9. The Tri-Level Inputs internal switching thresholds are approximately. 0.43V and 1.34V. It is advised to float the inputs, tie to ground or AVDD depending
on desired function.
10. The voltage is expressed in peak-to-peak differential swing. The peak-to-peak singled-ended swing is 1/2 of the differential swing.
Digital Specifications Boldface limits apply over the operating temperature range, -40°C to +85°C. (Continued)
PARAMETER
SYMBOL
CONDITIONS
MIN
(Note 5)
TYP
MAX
(Note 5)
UNITS
I2E Specifications Boldface limits apply over the operating temperature range, -40°C to +85°C.
PARAMETER
SYMBOL
CONDITIONS
MIN
(Note 5)
TYP
MAX
(Note 5)
UNITS
Offset Mismatch-induced Spurious Power
No I2E Calibration performed
-65
dBFS
Active Run state enabled
-70
dBFS
I2E Settling Times
I2Epost_t
Calibration settling time for
Active Run state
1000
ms
Minimum Duration of Valid Analog Input
tTE
Allow one I2E iteration of Offset,
Gain and Phase correction
100
µs
Largest Interleave Spur
fIN = 10MHz to 240MHz, Active
Run State enabled, in Track Mode
-99
dBc
fIN = 10MHz to 240MHz, Active
Run State enabled and previously
settled, in Hold Mode
-75
-80
dBc
fIN = 260MHz to 490MHz, Active
Run State enabled, in Track Mode
-99
dBc
fIN = 260MHz to 490MHz, Active
Run State enabled and previously
settled, in Hold Mode
-75
dBc
Total Interleave Spurious Power
Active Run State enabled, in
Track Mode, fIN is a broadband
signal in the 1st Nyquist zone
-85
dBc
Active Run State enabled, in
Track Mode, fIN is a broadband
signal in the 2nd Nyquist zone
-75
dBc
Sample Time Mismatch Between Unit ADCs
Active Run State enabled, in
Track Mode
25
fs
Gain Mismatch Between Unit ADCs
0.01
%FS
Offset Mismatch Between Unit ADCs
1mV


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