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ACE1202EM8X Fiches technique(PDF) 34 Page - Fairchild Semiconductor |
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ACE1202EM8X Fiches technique(HTML) 34 Page - Fairchild Semiconductor |
34 / 39 page 34 www.fairchildsemi.com ACE1202 Product Family Rev. B.1 Figure 35: HALT Register Definition Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 undefined undefined undefined undefined undefined undefined EIDLE EHALT Figure 34: Crystal (a) and RC (b) Oscillator Diagrams 33pF 33pF 1M CKI (G1) CKO (G0) a) C VCC R CKI (G1) CKO (G0) b) Normal Mode LD HALT, #01h Halt Multi-Input Wakeup LD PMC, #00h Resume Normal Mode Normal Mode CLR WKEN LD HALT, #02h IDLE LD PMC, #00h Resume Normal Mode Timer 0 Overflow 15.0 HALT Mode The HALT mode is a power saving feature that almost completely shuts down the device for current conservation. The device is placed into HALT mode by setting the HALT enable bit (EHALT) of the HALT register through software using only the “LD M, #” instruction. EHALT is a write only bit and is automatically cleared upon exiting HALT. When entering HALT, the internal oscillator and all the on-chip systems including the LBD and the BOR circuits are shut down. The device can exit HALT mode only by the MIW circuit. There- fore, prior to entering HALT mode, software must configure the MIW circuit accordingly. (See Section 9) After a wakeup from HALT, a 1ms start-up delay is initiated to allow the internal oscillator to stabilize before normal execution resumes. Immedi- ately after exiting HALT, software must clear the Power Mode Clear (PMC) register by only using the “LD M, #” instruction. (See Figure 36) 17.0 IDLE Mode In addition to the HALT mode power saving feature, the device also supports an IDLE mode operation. The device is placed into IDLE mode by setting the IDLE enable bit (EIDLE) of the HALT register through software using only the “LD M, #” instruction. EIDLE is a write only bit and is automatically cleared upon exiting IDLE. The IDLE mode operation is similar to HALT except the internal oscillator, the Watchdog, and the Timer 0 remain active while the other on-chip systems including the LBD and the BOR circuits are shut down. The device automatically wakes from IDLE mode by the Timer 0 overflow every 8192 cycles (see Section 6). Before entering IDLE mode, software must clear the WKEN register to disable the MIW block. Once a wake from IDLE mode is triggered, the core will begin normal operation by the next clock cycle. Immediately after exiting IDLE mode, software must clear the Power Mode Clear (PMC) register by using only the "LD M, #" instruction. (See Figure 37) Figure 36: Recommended HALT Flow Figure 37: Recommended IDLE Flow |
Numéro de pièce similaire - ACE1202EM8X |
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Description similaire - ACE1202EM8X |
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