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ACE1001LMT8X Fiches technique(PDF) 22 Page - Fairchild Semiconductor |
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ACE1001LMT8X Fiches technique(HTML) 22 Page - Fairchild Semiconductor |
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22 / 32 page  22 www.fairchildsemi.com ACE1001 Product Family Rev. B.1 8.0 Multi-Input Wakeup/Interrupt Block TheMulti-InputWakeup(MIW)/Interruptcontainsthreememory-mapped registers associated with this circuit: WKEDG (Wakeup Edge), WKEN (Wakeup Enable), and WKPND (Wakeup Pending). Each register has three bits with each bit corresponding to an input pins as shown in Figure 17. All three registers are initialized to zero upon reset. The WKEDG register establishes the edge sensitivity for each of the wake-up input pin: either (0) rising edge or (1) falling edge. The WKEN register enables (1) or disables (0) each of the port pins for the Wakeup/Interrupt function. The wakeup I/Os used for the Wakeup/Interrupt function must also be configured as an input pin in its associated port configuration register. However, an interrupt (EDGE1) of the core will not occur unless interrupts are enabled for the block via bit 7 of the T0CNTRL register (see Figure 15) and the G (global interrupt enable) bit of the SR is set. The WKPND register contains the pending flags corresponding to each of the port pins (1 for wakeup/interrupt pending, 0 for wakeup/interrupt not pending). TousetheMulti-InputWakeup/Interruptcircuit,performthestepslisted below. Performing the steps in the order shown will prevent false triggering of a Wakeup/Interrupt condition. This same procedure should be used following any type of reset because the wakeup inputs are left floating after resets resulting in unknown data on the port inputs. 1. Clear the WKEN register. - CLR WKEN 2. If necessary, write to the port configuration register to select the desired port pins to be configured as inputs. - RBIT 4, PORTGC ; G3, G4, and/or G5 3. If necessary, write to the port data register to select the desired port pins input state. - SBIT 4, PORTGD ; Pull-up 4. Write the WKEDG register to select the desired type of edge sensitivity for each of the pins used. - LD WKEDG, #38H ; Falling edges 5. Clear the WKPND register to cancel any pending bits. - CLR WKPND 6. Set the WKEN bits associated with the pins to be used, thus enabling those pins for the Wakeup/Interrupt function. - LD WKEN, #38H ; Enabling G3, G4, G5 Once the Multi-Input Wakeup/Interrupt function has been configured, a transition sensed on any of the enabled pins will set the correspond- ing bit in the WKPND register. The WKPND bits can bring the device out of the HALT/IDLE mode and can also trigger an interrupt if the interrupt is enabled. The interrupt service routine can read the WKPND register to determine which pin sensed the interrupt. The interrupt service routine or other software should clear the pending bit. The device will not enter HALT/IDLE mode as long as a WKPND pending bit is pending and enabled. The user has the responsibility of clearing the pending flags before attempting to enter the HALT/IDLE mode. Upon reset, the WKEDG register is configured to select positive- going edge sensitivity for all wakeup inputs. If the user wishes to change the edge sensitivity of a port pin, use the following proce- dure to avoid false triggering of a Wakeup/Interrupt condition. 1. Clear the WKEN bit associated with the pin to disable that pin. 2. Write the WKEDG register to select the new type of edge sensitivity for the pin. 3. Clear the WKPND bit associated with the pin. 4. Set the WKEN bit associated with the pin to re-enable it. PORTG provides the user with three fully selectable, edge sensi- tive interrupts that are all vectored into the same service subrou- tine. The interrupt from PORTG shares logic with the wakeup circuitry. The WKEN register allows interrupts from PORTG to be individually enabled or disabled. The WKEDG register specifies the trigger condition to be either a positive or a negative edge. The WKPND register latches in the pending trigger conditions. Since PORTG is also used for exiting the device from the HALT/ IDLE mode, the user can elect to exit the HALT/IDLE mode either with or without the interrupt enabled. If the user elects to disable the interrupt, then the device restarts execution from the point at which it was stopped (first instruction cycle of the instruction following HALT/IDLE mode entrance instruction). In the other case, the device finishes the instruction that was being executed when the part was stopped and then branches to the interrupt service routine. The device then reverts to normal operation. Data Bus 5 3 WKEN[5:3] 3 5 WKEDG[3:5] WKPND[3:5] G5 G3 EDGEI WKOUT 4 4 G4 WKINTEN8 Figure 18: Multi-input Wakeup (MIW) Block Diagram Figure 17: MIW Register Bit Assignments Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 x x G5 G4 G3 x x x 8 WKINTEN: Bit 7 of T0CNTRL |
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