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74VCX164245 Fiches technique(PDF) 2 Page - Fairchild Semiconductor

No de pièce 74VCX164245
Description  Low Voltage 16-Bit Dual Supply Translating Transceiver with 3-STATE Outputs
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Fabricant  FAIRCHILD [Fairchild Semiconductor]
Site Internet  http://www.fairchildsemi.com
Logo FAIRCHILD - Fairchild Semiconductor

74VCX164245 Fiches technique(HTML) 2 Page - Fairchild Semiconductor

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Connection Diagrams
Pin Assignment for TSSOP
Pin Assignment for FBGA
(Top Through View)
Pin Descriptions
FBGA Pin Assignments
Truth Tables
H
HIGH Voltage Level
L
LOW Voltage Level
X
Immaterial (HIGH or LOW, inputs may not float)
Z
High Impedance
Translator Power Up Sequence Recommendations
To guard against power up problems, some simple guide-
lines need to be adhered to. The VCX164245 is designed
so that the control pins (T/Rn, OEn) are supplied by VCCB.
Therefore the first recommendation is to begin by powering
up the control side of the device, VCCB. The OEn control
pins should be ramped with or ahead of VCCB, this will
guard against bus contentions and oscillations as all A Port
and B Port outputs will be disabled. To ensure the high
impedance state during power up or power down, OEn
should be tied to VCCB through a pull up resistor. The mini-
mum value of the resistor is determined by the current
sourcing capability of the driver. Second, the T/Rn control
pins should be placed at logic low (0V) level, this will
ensure that the B-side bus pins are configured as inputs to
help guard against bus contention and oscillations. B-side
Data Inputs should be driven to a valid logic level (0V or
VCCB), this will prevent excessive current draw and oscilla-
tions. VCCA can then be powered up after VCCB, but should
never exceed the VCCB voltage level. Upon completion of
these steps the device can then be configured for the users
desired operation. Following these steps will help to pre-
vent possible damage to the translator device as well as
other system components.
Pin Names
Description
OEn
Output Enable Input (Active LOW)
T/Rn
Transmit/Receive Input
A0–A15
Side A Inputs or 3-STATE Outputs
B0–B15
Side B Inputs or 3-STATE Outputs
NC
No Connect
12
3
4
5
6
A
B0
NC
T/R1
OE1
NC
A0
B
B2
B1
NC
NC
A1
A2
C
B4
B3
VCCB
VCCA
A3
A4
D
B6
B5
GND
GND
A5
A6
E
B8
B7
GND
GND
A7
A8
F
B10
B9
GND
GND
A9
A10
G
B12
B11
VCCB
VCCA
A11
A12
H
B14
B13
NC
NC
A13
A14
J
B15
NC
T/R2
OE2
NC
A15
Inputs
Outputs
OE1
T/R1
L
L
Bus B0–B7 Data to Bus A0–A7
L
H
Bus A0–A7 Data to Bus B0–B7
H
X
HIGH Z State on A0–A7, B0–B7
Inputs
Outputs
OE2
T/R2
L
L
Bus B8–B15 Data to Bus A8–A15
L
H
Bus A8–A15 Data to Bus B8–B15
H
X
HIGH-Z State on A8–A15, B8–B15


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