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74LVXC4245WMX Datasheet(Fiches technique) 5 Page - Fairchild Semiconductor

Numéro de pièce 74LVXC4245WMX
Description  8-Bit Dual Supply Configurable Voltage Interface Transceiver with 3-STATE Outputs
Télécharger  8 Pages
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Fabricant  FAIRCHILD [Fairchild Semiconductor]
Site Internet  http://www.fairchildsemi.com
Logo FAIRCHILD - Fairchild Semiconductor

74LVXC4245WMX Datasheet(HTML) 5 Page - Fairchild Semiconductor

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AC Electrical Characteristics
Note 6: Typical values at VCCA = 5V, VCCB = 5V @25°C.
Note 7: Typical values at VCCA = 5V, VCCB = 3.3V @25°C.
Note 8: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The
specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH). Parameter guaranteed by design.
Capacitance
Note 9: CPD is measured at 10 MHz.
Power Up Considerations
To insure the system does not experience unnecessary ICC
current draw, bus contention, or oscillations during power
up, the following guidelines should be adhered to (refer to
Table 1):
• Power up the control side of the device first. This is the
VCCA.
• OE should ramp with or ahead of VCCA. This will help
guard against bus contention.
• The Transmit/Receive control pin (T/R) should ramp with
VCCA, this will ensure that the A Port data pins are con-
figured as inputs. With VCCA receiving power first, the A
I/O Port should be configured as inputs to help guard
against bus contention and oscillations.
• A side data inputs should be driven to a valid logic level.
This will prevent excessive current draw.
The above steps will ensure that no bus contention or oscil-
lations, and therefore no excessive current draw occurs
during the power up cycling of these devices. These steps
will help prevent possible damage to the translator devices
and potential damage to other system components.
TABLE 1. Low Voltage Translator Power Up Sequencing Table
Please reference Application Note AN-5001 for more detailed information on using Fairchild’s LVX Low Voltage Dual
Supply CMOS Translating Transceivers.
Symbol
Parameter
CL = 50 pF
CL = 50 pF
Units
VCCA = 4.5V to 5.5V
VCCA = 4.5V to 5.5V
VCCB = 4.5V to 5.5V
VCCB = 2.7V to 3.6V
TA = +25°CTA = −40°C to +85°CTA = +25°CTA = −40°C to +85°C
Min
Typ
Max
Min
Max
Min
Typ
Max
Min
Max
(Note 6)
(Note 7)
tPHL
Propagation
1.0
4.9
6.5
1.0
7.0
1.0
5.5
7.5
1.0
8.0
ns
tPLH
Delay A to B
1.0
4.0
5.5
1.0
6.0
1.0
5.0
7.0
1.0
7.5
tPHL
Propagation
1.0
4.7
6.5
1.0
7.0
1.0
5.6
7.5
1.0
8.0
ns
tPLH
Delay B to A
1.0
3.9
5.0
1.0
5.5
1.0
4.3
6.0
1.0
6.5
tPZL
Output Enable
1.0
5.6
7.5
1.0
8.0
1.0
6.7
9.0
1.0
10.0
ns
tPZH
Time OE to B
1.0
5.7
7.5
1.0
8.0
1.0
6.9
9.5
1.0
10.0
tPZL
Output Enable
1.0
7.4
9.0
1.0
10.0
1.0
8.0
10.0
1.0
11.0
ns
tPZH
Time OE to A
1.0
6.1
7.5
1.0
8.5
1.0
6.3
8.0
1.0
8.5
tPHZ
Output Disable
1.0
4.8
7.0
1.0
7.5
1.0
6.0
9.0
1.0
9.5
ns
tPLZ
Time OE to B
1.0
3.8
5.5
1.0
6.0
1.0
4.2
6.5
1.0
7.0
tPHZ
Output Disable
1.0
3.4
5.5
1.0
6.0
1.0
3.4
5.5
1.0
6.0
ns
tPLZ
Time OE to A
1.0
2.9
4.5
1.0
5.0
1.0
2.9
5.0
1.0
5.5
tOSHL
Output to Output
tOSLH
Skew (Note 8)
1.0
1.5
1.5
1.0
1.5
1.5
ns
Data to Output
Symbol
Parameter
Typ
Units
Conditions
CIN
Input Capacitance
4.5
pF
VCC = Open
CI/O
Input/Output Capacitance
10
pF
VCCA = 5V, VCCB = 3.3V
CPD
Power Dissipation Capacitance
A
→B45
pF
VCCA = 5V
(Note 9)
B
→A50
pF
VCCB = 3.3V
Device Type
VCCA
VCCB
T/R
OE
A Side I/O
B Side I/O
Floatable Pin
Allowed
74LVXC4245
5V
2.7V to 5.5V
ramp
ramp
logic
outputs
yes, VCCB and B
(power up 1st)
configurable
with VCCA
with VCCA
0V or VCCA
I/O’s w/ OE HIGH


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