TCC-103A-PT datasheet(9/29 Pages) ONSEMI

No de pièce	TCC-103A-PT

Description	PTIC Control IC

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Fabricant	ONSEMI [ON Semiconductor]

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TCC−103

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9

Table 9. VIO THRESHOLDS

(AVDD from 2.3 V to 5.5 V; TA = –30 to +85°C unless otherwise specified)

Parameter

Description

Min

Typ

Max

Unit

Comment

VIORST

VIO Low Threshold

−

0.2

V

When VIO is lowered below this threshold level the

chip is reset and placed into the Shutdown state.

Power Supply Sequencing

The AVDD input is typically directly supplied from the

battery and thus is the first on. After AVDD is applied and

before VIO is applied to the chip all circuits are in the

shutdown state and draw minimum leakage currents. Upon

application of VIO the chip automatically starts up using

default settings and is placed in the active state waiting for

a command via the serial interface.

Table 10. TIMING

(AVDD from 2.3 V to 5.5 V; VIO from 1.1 V to 3.0 V; TA = –30 to +85°C; OUT A, OUT B & OUT C; CHV = 22 nF; LBOOST =15 mH;

VHV = 20 V; Turbo-Charge mode Off unless otherwise specified)

Parameter

Description

Min

Typ

Max

Unit

Comment

TPOR_VREG

Internal Bias settling time from Shutdown to Active

mode

−

50

120

ms

For Info Only

TBOOST_START

Time to charge CHV @ 95% of set VHV

−

130

−

ms

For Info Only

TSD_TO_ACT

Startup time from Shutdown to Active mode

−

180

250

ms

TSET+

Output A, B, C Positive settling time to within 5%

of the delta voltage, equivalent series load of

5.6 kW and 2.7 nF, VOUT from 2 V to 20 V; 0Bh

(11d) to 55h (85d)

−

50

60

ms

Voltage Settling Time

Connected on

VOUT A, B, C

TSET−

Output A, B, C Negative settling time to within 5%

of the delta voltage, equivalent series load of

5.6 kW and 2.7 nF, VOUT from 20 V to 2 V; 55h

(85d) to 0Bh (11d)

−

50

60

ms

Voltage Cettling Time

Connected on

VOUT A, B, C

Figure 4. Output Setting Diagram

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