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74LVX161284A Fiches technique(PDF) 5 Page - Fairchild Semiconductor

No de pièce 74LVX161284A
Description  Low Voltage IEEE 161284 Translating Transceiver
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Fabricant  FAIRCHILD [Fairchild Semiconductor]
Site Internet  http://www.fairchildsemi.com
Logo FAIRCHILD - Fairchild Semiconductor

74LVX161284A Fiches technique(HTML) 5 Page - Fairchild Semiconductor

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AC Electrical Characteristics
Note 8: tSKEW is measured for common edge output transitions and compares the measured propagation delay for a given path type:
(i) A1–A8 to B1–B8, A9–A13 to Y9–Y13
(ii) B1–B8 to A1–A8
(iii) C14–C17 to A14–A17
Capacitance
Note 9: CI/O is measured at frequency 1 MHz, per MIL-STD-883B, Method 3012
Symbol
Parameter
TA 40qC to  85qC
Units
Figure
Number
VCC 3.0V–3.6V
VCC—Cable 4.5V–5.5V
Min
Max
tPHL
A1–A8 to B1–B8
1.0
8.5
ns
Figure 1
tPLH
A1–A8 to B1–B8
1.0
8.5
ns
Figure 2
tPHL
B1–B8 to A1–A8
1.0
14.0
ns
Figure 3
tPLH
B1–B8 to A1–A8
1.0
14.0
ns
Figure 3
tPHL
A9–A13 to Y9–Y13
1.0
8.5
ns
Figure 1
tPLH
A9–A13 to Y9–Y13
1.0
8.5
ns
Figure 2
tPHL
C14–C17 to A14–A17
1.0
10.0
ns
Figure 3
tPLH
C14–C17 to A14–A17
1.0
10.0
ns
Figure 3
tSKEW
LH-LH or HL-HL
2.0
ns
(Note 8)
tPHL
PLHIN to PLH
1.0
8.5
ns
Figure 1
tPLH
PLHIN to PLH
1.0
8.5
ns
Figure 2
tPHL
HLHIN to HLH
1.0
10.0
ns
Figure 3
tPLH
HLHIN to HLH
1.0
12.0
ns
Figure 3
tPHZ
Output Disable Time
1.0
10.0
ns
Figure 4
tPLZ
DIR to A1–A8
1.0
10.0
tPZH
Output Enable Time
1.0
10.0
ns
Figure 5
tPZL
DIR to A1–A8
1.0
10.0
tPHZ
Output Disable Time
1.0
13.0
ns
Figure 6
tPLZ
DIR to B1–B8
1.0
10.0
tpEN
Output Enable Time
1.0
8.0
ns
Figure 2
HD to B1–B8, Y9–Y13
tpDIS
Output Disable Time
1.0
12.0
ns
Figure 2
HD to B1–B8, Y9–Y13
Symbol
Parameter
Typ
Units
Conditions
CIN
Input Capacitance
3
pF
VCC 0.0V (HD, DIR, A9–A13, C14–C17, PLHIN and HLHIN)
CI/O (Note 9)
I/O Pin Capacitance
5
pF
VCC 3.3V


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