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74FR25900SSC Datasheet(Fiches technique) 1 Page - Fairchild Semiconductor

Numéro de pièce 74FR25900SSC
Description  9-Bit, 3-Port Latchable Datapath Multiplexer with 25W Output Series Resistors
Télécharger  7 Pages
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Fabricant  FAIRCHILD [Fairchild Semiconductor]
Site Internet  http://www.fairchildsemi.com
Logo FAIRCHILD - Fairchild Semiconductor

74FR25900SSC Datasheet(HTML) 1 Page - Fairchild Semiconductor

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© 1999 Fairchild Semiconductor Corporation
DS011500
www.fairchildsemi.com
July 1992
Revised August 1999
74FR25900
9-Bit, 3-Port Latchable Datapath Multiplexer
with 25
Ω Output Series Resistors
General Description
The 74FR25900 is a data bus multiplexer routing any of
three 9-bit ports to any other one of the three ports. Read-
back of data latched from any port onto itself is also possi-
ble. The 74FR25900 maintains separate control of all latch-
enable, output enable and select inputs for maximum flexi-
bility. PINV allows inversion of the data from the C8 to A8 or
B8 path. This is useful for control of the parity bit in systems
diagnostics.
This device includes 25
Ω resistors in series with A and B
Port outputs. Resistors minimize undershoot and ringing
which may damage or corrupt sensitive device inputs
driven by these ports.
Features
s 25
Ω series resistors in the port A and B outputs elimi-
nate the need for external resistors when driving MOS
inputs such as DRAM arrays
s 9-bit data ports for systems carrying parity bits
s Readback capability for system self checks.
s Independent control lines for maximum flexibility
s Guaranteed multiple output switching and 250 pF load
delays
s Outputs optimized for dynamic bus drive capability
s PINV parity control facilitates system diagnostics
s 74FR900 option available without output series resistors
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbol
Pin Description
Connection Diagram
Order Number
Package Number
Package Description
74FR25900SSC
MS48A
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300 Wide
Pin Names
Description
LExx
Latch Enable Inputs
OEx
Output Enable Inputs
PINV
Parity Invert Input
S0, S1
Select Inputs
A0–A8
Port A Inputs or 3-STATE Outputs
B0–B8
Port B Inputs or 3-STATE Outputs
C0–C8
Port C Inputs or 3-STATE Outputs


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