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Moteur de recherche de fiches techniques de composants électroniques |
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Moteur de recherche de fiches techniques de composants électroniques |
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74F552SC Fiches technique(PDF) 3 Page - Fairchild Semiconductor |
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74F552SC Fiches technique(HTML) 3 Page - Fairchild Semiconductor |
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3 / 8 page  3 www.fairchildsemi.com Functional Description Data applied to the A-inputs are entered and stored in the R register on the rising edge of the CPR Clock Pulse, pro- vided that the Clock Enable (CER) is LOW; simultaneously, the status flip-flop is set and the flag (FR) output goes HIGH. As the Clock Enable (CER) returns to HIGH, the data will be held in the R register. These data entered from the A-inputs will appear at the B Port I/O pins after the Out- put Enable (OEBR) has gone LOW. When OEBR is LOW, a parity bit appears at the PARITY pin, which will be set HIGH when there is an even number of 1s or all 0s at the Q outputs of the R register. After the data is assimilated, the receiving system clears the flag FR by changing the signal at the OEBR pin from LOW-to-HIGH. Data flow from B-to-A proceeds in the same manner described for A-to-B flow. A LOW at the CES pin and a LOW-to-HIGH transition at CPS pin enters the B-input data and the parity-input data into the S registers and the parity register respectively and set the flag output FS to HIGH. A LOW signal at the OEAS pin enables the A Port I/O pins and a LOW-to-HIGH transition of the OEAS signal clears the FS flag. When OEAS is LOW, the parity check output ERROR will be HIGH if there is an odd number of 1s at the Q outputs of the S registers and the parity register. The flag FS can be cleared by a LOW-to-HIGH transition of the OEAS signal. Register Function Table (Applies to R or S Register) H = HIGH Voltage Level = LOW-to-HIGH Transition L = LOW Voltage Level † = Not LOW-to-HIGH Transition X = Immaterial NC = No Change Output Control H = HIGH Voltage Level X = Immaterial L = LOW Voltage Level Z = High Impedance Flag Flip-Flop Function Table (Applies to R or S Flag Flip-Flop) H = HIGH Voltage Level = LOW-to-HIGH Transition L = LOW Voltage Level † = Not LOW-to-HIGH Transition X = Immaterial NC = No Change Parity Generation Function H = HIGH Voltage Level X = Immaterial L = LOW Voltage Level Z = High Impedance Parity Check Function H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Inputs Internal Function DCP CE Q XX H NC Hold Data L LL Load Data H LH X † L NC Keep Old Data OE Internal A or B Function Q Outputs H X Z Disable Output L L L Enable Output L H H Enable Output Inputs Flag Function CE CP OE Output H X † NC Hold Flag L †H Set Flag XX L Clear Flag OEBR Number of HIGHs in the Parity Output Q Outputs of the R Register HX Z L 0, 2, 4, 6, 8 H L 1, 3, 5, 7 L OEAS Number of HIGHs in Parity ERROR the Q Outputs of the S Register Input Output HX X H L 0, 2, 4, 6, 8 L L L 1, 3, 5, 7 L H L 0, 2, 4, 6, 8 H H L 1, 3, 5, 7 H L |
Numéro de pièce similaire - 74F552SC |
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Description similaire - 74F552SC |
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