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74F533 Fiches technique(PDF) 2 Page - Fairchild Semiconductor

No de pièce 74F533
Description  Octal Transparent Latch with 3-STATE Outputs
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Fabricant  FAIRCHILD [Fairchild Semiconductor]
Site Internet  http://www.fairchildsemi.com
Logo FAIRCHILD - Fairchild Semiconductor

74F533 Fiches technique(HTML) 2 Page - Fairchild Semiconductor

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Unit Loading/Fan Out
Function Table
H
= HIGH Voltage Level
L
= LOW Voltage Level
X
= Immaterial
Functional Description
The 74F533 contains eight D-type latches with 3-STATE
output buffers. When the Latch Enable (LE) input is HIGH,
data on the Dn inputs enters the latches. In this condition
the latches are transparent, i.e., a latch output will change
state each time its D input changes. When LE is LOW, the
latches store the information that was present on the D
inputs a setup time preceding the HIGH-to-LOW transition
of LE. The 3-STATE buffers are controlled by the Output
Enable (OE) input. When OE is LOW, the buffers are in the
bi-state mode. When OE is HIGH the buffers are in the high
impedance mode but this does not interfere with entering
new data into the latches.
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
Pin Names
Description
U.L.
Input IIH/IIL
HIGH/LOW
Output IOH/IOL
D0–D7
Data Inputs
1.0/1.0
20
µA/−0.6 mA
LE
Latch Enable Input (Active HIGH)
1.0/1.0
20
µA/−0.6 mA
OE
Output Enable Input (Active LOW)
1.0/1.0
20
µA/−0.6 mA
O0–O7
Complementary 3-STATE Outputs
150/40 (33.3)
−3 mA/24 mA (20 mA)
Inputs
Output
LE
OE
DO
HL
H
L
HL
L
H
LL
X
O0
XHX
Z


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