Moteur de recherche de fiches techniques de composants électroniques
  French  ▼

Delete All
ON OFF
ALLDATASHEET.FR

X  

Preview PDF Download HTML

74F373 Fiches technique(PDF) 2 Page - Fairchild Semiconductor

No de pièce 74F373
Description  Octal Transparent Latch with 3-STATE Outputs
Download  8 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Fabricant  FAIRCHILD [Fairchild Semiconductor]
Site Internet  http://www.fairchildsemi.com
Logo FAIRCHILD - Fairchild Semiconductor

74F373 Fiches technique(HTML) 2 Page - Fairchild Semiconductor

  74F373 Datasheet HTML 1Page - Fairchild Semiconductor 74F373 Datasheet HTML 2Page - Fairchild Semiconductor 74F373 Datasheet HTML 3Page - Fairchild Semiconductor 74F373 Datasheet HTML 4Page - Fairchild Semiconductor 74F373 Datasheet HTML 5Page - Fairchild Semiconductor 74F373 Datasheet HTML 6Page - Fairchild Semiconductor 74F373 Datasheet HTML 7Page - Fairchild Semiconductor 74F373 Datasheet HTML 8Page - Fairchild Semiconductor  
Zoom Inzoom in Zoom Outzoom out
 2 / 8 page
background image
www.fairchildsemi.com
2
Unit Loading/Fan Out
Functional Description
The 74F373 contains eight D-type latches with 3-STATE
output buffers. When the Latch Enable (LE) input is HIGH,
data on the Dn inputs enters the latches. In this condition
the latches are transparent, i.e., a latch output will change
state each time its D input changes. When LE is LOW, the
latches store the information that was present on the D
inputs a setup time preceding the HIGH-to-LOW transition
of LE. The 3-STATE buffers are controlled by the Output
Enable (OE) input. When OE is LOW, the buffers are in the
bi-state mode. When OE is HIGH the buffers are in the high
impedance mode but this does not interfere with entering
new data into the latches.
Truth Table
H
= HIGH Voltage Level
L
= LOW Voltage Level
X
= Immaterial
Z
= High Impedance State
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
Pin Names
Description
U.L.
Input IIH/IIL
HIGH/LOW
Output IOH/IOL
D0–D7
Data Inputs
1.0/1.0
20
µA/−0.6 mA
LE
Latch Enable Input (Active HIGH)
1.0/1.0
20
µA/−0.6 mA
OE
Output Enable Input (Active LOW)
1.0/1.0
20
µA/−0.6 mA
O0–O7
3-STATE Latch Outputs
150/40 (33.3)
−3 mA/24 mA (20 mA)
Inputs
Output
LE
OE
Dn
On
HL
H
H
HL
L
L
LL
X
On (no change)
XHX
Z


Html Pages

1  2  3  4  5  6  7  8 


Fiches technique Télécharger

Go To PDF Page


Lien URL




Politique de confidentialité
ALLDATASHEET.FR
ALLDATASHEET vous a-t-il été utile ?  [ DONATE ] 

À propos de Alldatasheet   |   Publicité   |   Contactez-nous   |   Politique de confidentialité   |   Echange de liens   |   Fabricants
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn