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74ACTQ74 Fiches technique(PDF) 3 Page - Fairchild Semiconductor

No de pièce 74ACTQ74
Description  Quiet Series Dual D-Type Positive Edge-Triggered Flip-Flop
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Fabricant  FAIRCHILD [Fairchild Semiconductor]
Site Internet  http://www.fairchildsemi.com
Logo FAIRCHILD - Fairchild Semiconductor

74ACTQ74 Fiches technique(HTML) 3 Page - Fairchild Semiconductor

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Absolute Maximum Ratings(Note 1)
Recommended Operating
Conditions
Note 1: Absolute maximum ratings are those values beyond which dam-
age to the device may occur. The databook specifications should be met,
without exception, to ensure that the system design is reliable over its
power supply, temperature, and output/input loading variables. Fairchild
does not recommend operation of FACT
 circuits outside databook specifi-
cations.
DC Electrical Characteristics
Note 2: All outputs loaded; thresholds on input associated with output under test.
Note 3: Maximum test duration 2.0 ms, one output loaded at a time.
Note 4: PDIP package.
Note 5: Max number of outputs defined as (n). Data inputs are driven 0V to 3V. One output @ GND.
Note 6: Max number of data inputs (n) switching. (n
− 1) inputs switching 0V to 3V. Input-under-test switching:
3V to threshold (VILD), 0V to threshold (VIHD), f = 1 MHz.
Supply Voltage (VCC)
−0.5V to +7.0V
DC Input Diode Current (IIK)
VI = −0.5V
−20 mA
VI = VCC + 0.5V
+20 mA
DC Input Voltage (VI)
−0.5V to V
CC + 0.5V
DC Output Diode Current (IOK)
VO = −0.5V
−20 mA
VO = VCC + 0.5V
+20 mA
DC Output Voltage (VO)
−0.5V to V
CC + 0.5V
DC Output Source
or Sink Current (IO)
± 50 mA
DC VCC or Ground Current
per Output Pin (ICC or IGND)
± 50 mA
Storage Temperature (TSTG)
−65°C to +150°C
DC Latch-Up Source or Sink Current
± 300 mA
Junction Temperature (TJ) PDIP
140
°C
Supply Voltage (VCC)
4.5V to 5.5V
Input Voltage (VI)
0V to VCC
Output Voltage (VO)
0V to VCC
Operating Temperature (TA)
−40°C to +85°C
Minimum Input Edge Rate
∆V/∆t
VIN from 0.8V to 2.0V
VCC @ 4.5V, 5.5V
125 mV/ns
Symbol
Parameter
VCC
TA = +25°C
TA = −40°C to +85°C
Units
Conditions
(V)
Typ
Guaranteed Limits
VIH
Minimum HIGH Level
4.5
1.5
2.0
2.0
V
VOUT = 0.1V
Input Voltage
5.5
1.5
2.0
2.0
or VCC − 0.1V
VIL
Maximum LOW Level
4.5
1.5
0.8
0.8
V
VOUT = 0.1V
Input Voltage
5.5
1.5
0.8
0.8
or VCC − 0.1V
VOH
Minimum HIGH Level
4.5
4.49
4.4
4.4
VIOUT = −50 µA
Output Voltage
5.5
5.49
5.4
5.4
4.5
3.86
3.76
V
VIN = VIL or VIH
IOH = −24 mA
IOH = −24 mA (Note 2)
5.5
4.86
4.76
VOL
Maximum LOW Level
4.5
0.001
0.1
0.1
VIOUT = 50 µA
Output Voltage
5.5
0.001
0.1
0.1
4.5
0.36
0.44
V
VIN = VIL or VIH
IOL = 24 mA
IOL = 24 mA (Note 2)
5.5
0.36
0.44
IIN
Maximum Input Leakage Current
5.5
± 0.1
± 1.0
µAV
I = VCC, GND
IOZ
Maximum 3-STATE
5.5
± 0.5
± 5.0
µA
VI = VIL, VIH
Leakage Current
VO = VCC, GND
ICCT
Maximum ICC/Input
5.5
0.6
1.5
mA
VI = VCC − 2.1V
IOLD
Minimum Dynamic
5.5
75
mA
VOLD = 1.65V Max
IOHD
Output Current (Note 2)
5.5
−75
mA
VOHD = 3.85V Min
ICC
Maximum Quiescent Supply Current
5.5
2.0
20.0
µAV
IN = VCC or GND
VOLP
Quiet Output Maximum
5.0
1.1
1.5
V
Figure 1, Figure 2
Dynamic VOL
(Note 4)(Note 5)
VOLV
Quiet Output Minimum
5.0
−0.6
−1.2
V
Figure 1, Figure 2
Dynamic VOL
(Note 4)(Note 5)
VIHD
Minimum HIGH Level Dynamic Input Voltage
5.0
1.9
2.2
V
(Note 4)(Note 6)
VILD
Maximum LOW Level Dynamic Input Voltage
5.0
1.2
0.8
V
(Note 4)(Note 6)


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