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AD5263BRUZ200 Fiches technique(PDF) 5 Page - Analog Devices

No de pièce AD5263BRUZ200
Description  Quad, 15 V, 256-Position, Digital Potentiometer with Pin-Selectable SPI/I2C
Download  28 Pages
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Fabricant  AD [Analog Devices]
Site Internet  http://www.analog.com
Logo AD - Analog Devices

AD5263BRUZ200 Fiches technique(HTML) 5 Page - Analog Devices

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Data Sheet
AD5263
Rev. F | Page 5 of 28
TIMING CHARACTERISTICS—20 kΩ, 50 kΩ, 200 kΩ VERSIONS
VDD = +5 V, VSS = –5 V, VL = +5 V, VA = +VDD, VB = 0 V, –40°C < TA < +125°C, unless otherwise noted.
Table 2.
Parameter
Symbol
Conditions
Min
Typ1
Max
Unit
SPI INTERFACE TIMING CHARACTERISTICS
Specifications apply to all parts2, 3
Clock Frequency
f
CLK
25
MHz
Input Clock Pulse Width
t
CH, tCL
Clock level high or low
20
ns
Data Setup Time
t
DS
10
ns
Data Hold Time
t
DH
10
ns
CS Setup Time
t
CSS
15
ns
CS High Pulse Width
t
CSW
20
ns
CLK Fall to CS Fall Hold Time
t
CSH0
0
ns
CLK Fall to CS Rise Hold Time
t
CSH1
0
ns
CS Rise to Clock Rise Setup
t
CS1
10
ns
Reset Pulse Width
t
RS
5
ns
I2C INTERFACE TIMING CHARACTERISTICS
Specifications apply to all parts2, 3
SCL Clock Frequency
f
SCL
400
kHz
t
BUF Bus Free Time Between Stop and Start
t
1
1.3
µs
t
HD;STA Hold Time (Repeated Start)
t
2
After this period, the first clock
pulse is generated.
0.6
µs
t
LOW Low Period of SCL Clock
t
3
1.3
µs
t
HIGH High Period of SCL Clock
t
4
0.6
50
µs
t
SU;STA Setup Time for Start Condition
t
5
0.6
µs
t
HD;DAT Data Hold Time
t
6
0.9
µs
t
SU;DAT Data Setup Time
t
7
100
ns
t
F Fall Time of Both SDA and SCL Signals
t
8
300
ns
t
R Rise Time of Both SDA and SCL Signals
t
9
300
ns
t
SU;STO Setup Time for Stop Condition
t
10
0.6
µs
1 Typicals represent average readings at +25°C and V
DD = +5 V, VSS = −5 V
2 Guaranteed by design and not subject to production test.
3 See timing diagrams for location of measured values. All input control voltages are specified with t
R = tF = 2 ns (10% to 90% of 3 V) and timed from a voltage level
of 1.5 V. Switching characteristics are measured using VL = 5 V.


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