FW323 datasheet(5/152 Pages) AGERE

No de pièce	FW323

Description	1394A PCI PHY/Link Open Host Controller Interface

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Agere Systems Inc.

5

Data Sheet, Rev. 2

FW323 05

October 2001

1394A PCI PHY/Link Open Host Controller Interface

Table of Contents (continued)

Table

Page

Table 52. GUID High Register ................................................................................................................................64

Table 53. GUID High Register Description .............................................................................................................65

Table 54. GUID Low Register .................................................................................................................................66

Table 55. GUID Low Register Description ..............................................................................................................67

Table 56. Configuration ROM Mapping Register ....................................................................................................68

Table 57. Configuration ROM Mapping Register Description .................................................................................69

Table 58. Posted Write Address Low Register .......................................................................................................70

Table 59. Posted Write Address Low Register Description ....................................................................................71

Table 60. Posted Write Address High Register ......................................................................................................72

Table 61. Posted Write Address High Register Description ...................................................................................73

Table 62. Vendor ID Register .................................................................................................................................74

Table 63. Vendor ID Register Description ..............................................................................................................75

Table 64. Host Controller Control Register .............................................................................................................76

Table 65. Host Controller Control Register Description ..........................................................................................77

Table 66. Self-ID Buffer Pointer Register ...............................................................................................................78

Table 67. Self-ID Buffer Pointer Register Description ............................................................................................79

Table 68. Self-ID Count Register ............................................................................................................................80

Table 69. Self-ID Count Register Description .........................................................................................................81

Table 70. Isochronous Receive Channel Mask High Register ...............................................................................82

Table 71. Isochronous Receive Channel Mask High Register Description ............................................................83

Table 72. Isochronous Receive Channel Mask Low Register ................................................................................84

Table 73. Isochronous Receive Channel Mask Low Register Description ............................................................85

Table 74. Interrupt Event Register ..........................................................................................................................86

Table 75. Interrupt Event Register Description .......................................................................................................87

Table 76. Interrupt Mask Register ..........................................................................................................................89

Table 77. Interrupt Mask Register Description .......................................................................................................90

Table 78. Isochronous Transmit Interrupt Event Register ......................................................................................91

Table 79. Isochronous Transmit Interrupt Event Register Description ...................................................................92

Table 80. Isochronous Transmit Interrupt Mask Register .......................................................................................93

Table 81. Isochronous Receive Interrupt Event Register .......................................................................................94

Table 82. Isochronous Receive Interrupt Event Description ..................................................................................95

Table 83. Isochronous Receive Interrupt Mask Register ........................................................................................96

Table 84. Fairness Control Register .......................................................................................................................97

Table 85. Fairness Control Register Description ....................................................................................................98

Table 86. Link Control Register .............................................................................................................................99

Table 87. Link Control Register Description ........................................................................................................100

Table 88. Node Identification Register .................................................................................................................101

Table 89. Node Identification Register Description ..............................................................................................102

Table 90. PHY Core Layer Control Register ........................................................................................................103

Table 91. PHY Core Layer Control Register Description .....................................................................................104

Table 92. Isochronous Cycle Timer Register .......................................................................................................105

Table 93. Isochronous Cycle Timer Register Description ....................................................................................106

Table 94. Asychronous Request Filter High Register ..........................................................................................107

Table 95. Asynchronous Request Filter High Register Description ......................................................................108

Table 96. Asynchronous Request Filter Low Register ........................................................................................110

Table 97. Asynchronous Request Filter Low Register Description ......................................................................111

Table 98. Physical Request Filter High Register ..................................................................................................113

Table 99. Physical Request Filter High Register Description ...............................................................................114

Table 100. Physical Request Filter Low Register ................................................................................................116

Table 101. Physical Request Filter Low Register Description ..............................................................................117

Table 102. Asynchronous Context Control Register ............................................................................................119

Numéro de pièce similaire - FW323

Fabricant	No de pièce	Fiches technique	Description
Agere Systems	FW32306	1Mb / 92P	PCI PHY/Link Open Host Controller Interface
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Description similaire - FW323

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Agere Systems	FW322	1Mb / 148P	1394A PCI PHY/Link Open Host Controller Interface
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VIA Technologies, Inc.	VT6307	449Kb / 54P	PCI 1394a-2000 Integrated Host Controller
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	TSB43AB21	656Kb / 109P	[Old version datasheet] INTERGRATED 1394A-2000 OHCI PHY LINK-LAYER CONTROLLER
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