TPS53015

SW

DRVL

DRVH

VBST

EN

VFB

VREG5

PG

PGND

VIN

1

2

3

4

5

6

7

8

9

10

TPS53015

www.ti.com

SLVSBF0B – JULY 2012 – REVISED AUGUST 2012

PIN FUNCTIONS

PIN

I/O

DESCRIPTION

NAME

VSSOP-10

VFB

1

I

D-CAP2 feedback input. Connect to output voltage with resistor divider.

PG

2

O

Open drain power good output.

VREG5

3

O

Output of 5-V linear regulator and supply for MOSFET driver. Bypass to GND with a minimum 4.7-

μF high

quality ceramic capacitor. VREG5 is active when EN is asserted high.

EN

4

I

Enable. Pull High to enable converter.

VIN

5

I

Supply Input for 5-V linear regulator. Bypass to GND with a minimum 0.1-

μF high quality ceramic capacitor.

PGND

6

I

System ground.

DRVL

7

O

Low-side N-Channel MOSFET gate driver output. PGND referenced driver switches between PGND(OFF)

and VREG5(ON).

SW

8

I/O

Switch node connections for both the high-side driver and over current comparator.

High-side N-channel MOSFET gate driver output. SW referenced driver switches between SW(OFF) and

DRVH

9

O

VBST(ON).

High-side MOSFET gate driver bootstrap voltage input. Connect a capacitor from VBST to SW. An internal

VBST

10

I

diode is connected between VREG5 and VBST

10 PIN VSSOP

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