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TPS25910RSAT Fiches technique(PDF) 3 Page - Texas Instruments

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No de pièce TPS25910RSAT
Description  3-V to 20-V High-Current Load Switch with Programmable Inrush Slew Rate
Download  25 Pages
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Fabricant  TI [Texas Instruments]
Site Internet  http://www.ti.com
Logo TI - Texas Instruments

TPS25910RSAT Fiches technique(HTML) 3 Page - Texas Instruments

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TPS25910
www.ti.com
SLUSAR6B – SEPTEMBER 2012 – REVISED MARCH 2013
RECOMMENDED OPERATING CONDITIONS
over device junction temperature range (unless otherwise noted)
PARAMETER
MIN
NOM
MAX
UNIT
Input voltage range IN, OUT
3
20
Voltage range EN
0
5
V
Voltage range FLT
0
20
Continuous output current IOUT
0
5
A
Output sink current FLT
0
1
mA
External Capacitor, GATE
1
47
nF
dv/dt, VIN
(1)
12
V/
μS
RLIM
(2)
0
237k
Ω
Junction temperature
-40
125
°C
(1)
dV/dt, VIN should be limited to 12 V/μS to confine the shoot-through current to the load.
(2)
When RLIM value is beyond this range, ILIM will not be as accurate as within this range.
THERMAL INFORMATION
TPS25910
THERMAL METRIC(1)
RSA (QFN)
UNITS
16 PINS
θJA
Junction-to-ambient thermal resistance(2)
34.8
θJCtop
Junction-to-case (top) thermal resistance(3)
35.3
θJB
Junction-to-board thermal resistance(4)
11.9
°C/W
ψJT
Junction-to-top characterization parameter(5)
0.4
ψJB
Junction-to-board characterization parameter(6)
12.0
θJCbot
Junction-to-case (bottom) thermal resistance(7)
3.3
(1)
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2)
The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
(3)
The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-
standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(4)
The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
(5)
The junction-to-top characterization parameter,
ψJT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining
θJA, using a procedure described in JESD51-2a (sections 6 and 7).
(6)
The junction-to-board characterization parameter,
ψJB, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining
θJA , using a procedure described in JESD51-2a (sections 6 and 7).
(7)
The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
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