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TPD5S115YFFR Fiches technique(PDF) 11 Page - Texas Instruments |
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TPD5S115YFFR Fiches technique(HTML) 11 Page - Texas Instruments |
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11 / 23 page  TPD5S115 www.ti.com SLVSBL2B – OCTOBER 2012 – REVISED MARCH 2013 SWITCHING CHARACTERISTICS (continued) over operating free-air temperature range (unless otherwise noted) PARAMETER PINS TEST CONDITIONS MIN TYP MAX UNIT TRISE B port rise time B-Port CEC channels enabled 16 µs Section 3.2C (Voltage Level Shifter- HPD Line (x_A & x_B ports) VCCA = 1.5V TPHL Propagation delay B to A CEC channels enabled 10 ns TPLH Propagation delay B to A CEC channels enabled 10 ns TFALL A port fall time A-Port CEC channels enabled 0.46 ns TRISE A port rise time A-Port CEC channels enabled 0.5 ns Section 3.3A (Voltage Level Shifter- SCL, SDA Lines (x_A & x_B ports) VCCA = 1.8V A to B DDC channels enabled 370 ns TPHL Propagation delay B to A DDC channels enabled 230 ns A to B DDC channels enabled 480 ns TPLH Propagation delay B to A DDC channels enabled 163 ns TFALL A port fall time A-Port DDC channels enabled 100 ns TFALL B port fall time B-Port DCC channels enabled 135 ns TRISE A port rise time A-Port DCC channels enabled 180 ns TRISE B port rise time B-Port DCC channels enabled 93 ns FMAX Maximum switching frequency DCC channels enabled 400 kHz Section 3.3B (Voltage Level Shifter- CEC Line (x_A & x_B ports) VCCA = 1.8V A to B CEC channels enabled 530 ns TPHL Propagation delay B to A CEC channels enabled 230 ns A to B CEC channels enabled 13 µs TPLH Propagation delay B to A CEC channels enabled 280 ns TFALL A port fall time A-Port CEC channels enabled 98 ns TFALL B port fall time B-Port CEC channels enabled 200 ns TRISE A port rise time A-Port CEC channels enabled 180 ns TRISE B port rise time B-Port CEC channels enabled 16 µs Section 3.3C (Voltage Level Shifter- HPD Line (x_A & x_B ports) VCCA = 1.8V TPHL Propagation delay B to A CEC channels enabled 10 ns TPLH Propagation delay B to A CEC channels enabled 10 ns TFALL A port fall time A-Port CEC channels enabled 0.41 ns TRISE A port rise time A-Port CEC channels enabled 0.41 ns Section 3.4A (Voltage Level Shifter- SCL, SDA Lines (x_A & x_B ports) VCCA = 2.5V A to B DDC channels enabled 370 ns TPHL Propagation delay B to A DDC channels enabled 185 ns A to B DDC channels enabled 467 ns TPLH Propagation delay B to A DDC channels enabled 160 ns TFALL A port fall time A-Port DDC channels enabled 80 ns TFALL B port fall time B-Port DCC channels enabled 135 ns TRISE A port rise time A-Port DCC channels enabled 179 ns TRISE B port rise time B-Port DCC channels enabled 93 ns FMAX Maximum switching frequency DCC channels enabled 400 kHz Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback 11 Product Folder Links: TPD5S115 |
Numéro de pièce similaire - TPD5S115YFFR |
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Description similaire - TPD5S115YFFR |
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