REV. 0

ADN2841

–7–

The second photodiode current is mirrored to IMPDMON2

for wavelength control purposes and is summed internally for

the power control loop.

For single MPD circuits the MPD2 pin

is tied to GND.

This enables the system designer to use the two currents to

control the wavelength of the laser diode using various optical

filtering techniques inside the laser module.

If the monitor current functions IMPDMON and IMPDMON2

are not required, the IMPD and IMPD2 pins can be grounded

and the monitor photodiode output can be connected di-

rectly to PSET.

IDTONE (48-PIN LFCSP ONLY)

The IDTONE pin is supplied for fiber identification/supervisory

channels or control purposes in WDM. This pin modulates the

optical one level over a possible range of 2% of minimum IMOD

to 10% of maximum IMOD. The level of modulation is set by

connecting an external current sink between the IDTONE pin and

ground. There is a gain of two from this pin to the IMOD current.

Figure 3 shows how an AD9850/AD9851 DDS may be used

with the ADN2841 to allow fiber identification.

Note that using IDTONE during transmission may cause opti-

cal eye degradation.

DATA, CLOCK INPUTS

Data and Clock inputs are ac-coupled (10 nF recommended)

and terminated via a 100

Ω internal resistor between DATAP

and DATAN, and also between CLKP and CLKN pins. There

is a high-impedance circuit to set the common-mode voltage

that is designed to change over temperature. It is recommended

that ac coupling be used to eliminate the need for matching

between common-mode voltages.

Figure 4. AC Coupling of Data Inputs

CCBIAS

CCBIAS should be connected to the BIAS pin if the laser diode is

connected to the ADN2841 using a capacitor. CCBIAS is a

current sink to GND.

AUTOMATIC LASER SHUTDOWN

The ADN2841 ALS allows compliance to ITU-T-G958

(11/94), section 9.7.

When ALS is logic high, both bias and modulation currents are

turned off.

Correct operation of ALS can be confirmed by the fail alarm

being raised when ALS is asserted. Note this is the only time

that DEGRADE will be low while FAIL is high.

Figure 3. Circuitry to Allow Fiber Identification

REF CLOCK

20MHz–

180MHz

CLKIN

AD9850/AD9851

DDS

1.25mA–20mA

50

50

LP FILTER

(DC-COUPLED)

AD8602

10kHz–1MHz

0.125mA–2mA

BC550

500

50 A–800 A

1000

1300

BC550

37.5 A–600 A

IDTONE

ADN2841

IMMON

CONTROLLER

1/2

AD8602

1/2

ADN2841

R = 2.5k , DATA

R = 3k , CLK

TO FLIP-FLOPS

400 A TYP

DATAP

DATAN

R

50

50