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ADM8693AN Fiches technique(PDF) 7 Page - Analog Devices

No de pièce ADM8693AN
Description  Microprocessor Supervisory Circuits
Download  16 Pages
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Fabricant  AD [Analog Devices]
Site Internet  http://www.analog.com
Logo AD - Analog Devices

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ADM8690–ADM8695
REV. 0
–7–
Table I. ADM8691, ADM8693, ADM8695 Reset Pulse Width and Watchdog Timeout Selections
Watchdog Timeout Period
Reset Active Period
Immediately
OSC SEL
OSC IN
Normal
After Reset
ADM8691/ADM8693
ADM8695
Low
External Clock Input
1024 CLKS
4096 CLKS
512 CLKS
2048 CLKS
Low
External Capacitor
400 ms
× C/47 pF
1.6 s
× C/47 pF
200 ms
× C/47 pF
520 ms
× C/47 pF
Floating or High
Low
100 ms
1.6 s
50 ms
200 ms
Floating or High
Floating or High
1.6 s
1.6 s
50 ms
200 ms
NOTE
With the OSC SEL pin low, OSC IN can be driven by an external clock signal, or an external capacitor can be connected between OSC IN and GND. The nominal
internal oscillator frequency is 10.24 kHz. The nominal oscillator frequency with external capacitor is: F OSC (Hz) = 184,000/C (pF)
On the ADM8690/ADM8692 the watchdog timeout period is
fixed at 1.6 seconds and the reset pulse width is fixed at 50 ms.
On the ADM8694 the watchdog timeout period is also 1.6 sec-
onds but the reset pulse width is fixed at 200 ms. The ADM8691/
ADM8693/ADM8695 allow these times to be adjusted as
shown in Table I. Figure 4 shows the various oscillator configu-
rations that can be used to adjust the reset pulse width and
watchdog timeout period.
The internal oscillator is enabled when OSC SEL is high or
floating. In this mode, OSC IN selects between the 1.6 second
and 100 ms watchdog timeout periods. With OSC IN connected
high or floating, the 1.6 second timeout period is selected; while
with it connected low, the 100 ms timeout period is selected. In
either case, immediately after a reset the timeout period is 1.6
seconds. This gives the microprocessor time to reinitialize the
system. If OSC IN is low, then the 100 ms watchdog period be-
comes effective after the first transition of WDI. The software
should be written such that the I/O port driving WDI is left in
its power-up reset state until the initialization routines are com-
pleted and the microprocessor is able to toggle WDI at the mini-
mum watchdog timeout period of 70 ms.
Watchdog Output (WDO)
The Watchdog Output
WDO (ADM8691/ADM8693/
ADM8695) provides a status output which goes low if the
watchdog timer “times out” and remains low until set high by
the next transition on the Watchdog Input.
WDO is also set
high when VCC goes below the reset threshold.
8
7
CLOCK
0 TO 500kHz
OSC SEL
OSC IN
ADM8691
ADM8693
ADM8695
Figure 4a. External Clock Source
8
7
OSC SEL
OSC IN
ADM8691
ADM8693
ADM8695
COSC
Figure 4b. External Capacitor
8
7
NC
NC
OSC SEL
OSC IN
ADM8691
ADM8693
ADM8695
Figure 4c. Internal Oscillator (1.6 Second Watchdog)
8
7
OSC SEL
OSC IN
ADM8691
ADM8693
ADM8695
NC
Figure 4d. Internal Oscillator (100 ms Watchdog)


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