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ADM1486JN Fiches technique(PDF) 2 Page - Analog Devices |
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ADM1486JN Fiches technique(HTML) 2 Page - Analog Devices |
2 / 8 page REV. B –2– ADM1486–SPECIFICATIONS (V CC = +5 V ± 5%. All specifications TMIN to TMAX unless otherwise noted.) Parameter Min Typ Max Unit Test Conditions/Comments DRIVER Differential Output Voltage, VOD 5.0 V R = Infinity, Figure 1 2.0 5.0 V VCC = 5 V, R = 50 (RS-422), Figure 1 2.1 5.0 V R = 27 (RS-485), Figure 1 V OD3 2.1 5.0 V VTST = –7 V to +12 V, Figure 2 |VOD| for Complementary Output States 0.2 V R = 27 or 50 , Figure 1 Common-Mode Output Voltage VOC 3 V R = 27 or 50 , Figure 1 |VOD| for Complementary Output States 0.2 V R = 27 or 50 Output Short Circuit Current(VOUT=High) 60 150 m A –7 V VO +12 V Output Short Circuit Current(VOUT=Low) 60 150 m A –7 V VO +12 V CMOS Input Logic Threshold Low, VINL 0.8 V CMOS Input Logic Threshold High, VINH 2.0 V Logic Input Current (DE, DI) ±1.0 µ A RECEIVER Differential Input Threshold Voltage, VTH –0.2 +0.2 V –7 V VCM +12 V Input Voltage Hysteresis, VTH 70 m V VCM = 0 V Input Resistance 20 k –7 V VCM +12 V Input Current (A, B) + 1 m A VIN = 12 V –0.8 m A VIN = –7 V Logic Enable Input Current ( RE)± 1 µ A CMOS Output Voltage Low, VOL 0.4 V IOUT = +4.0 mA CMOS Output Voltage High, VOH 4.0 V IOUT = –4.0 mA Short Circuit Output Current 7 85 m A VOUT = GND or VCC Tristate Output Leakage Current ±1.0 µ A 0.4 V VOUT +2.4 V POWER SUPPLY CURRENT ICC (Outputs Enabled) 1.2 2.0 m A Outputs Unloaded, Digital Inputs = GND or VCC ICC (Outputs Disabled) 0.9 1.5 m A Outputs Unloaded, Digital Inputs = GND or VCC Specifications subject to change without notice. TIMING SPECIFICATIONS (V CC = +5 V ± 5%. All specifications TMIN to TMAX unless otherwise noted.) Parameter Min Typ Max Unit Test Conditions/Comments DRIVER Propagation Delay Input to Output TPLH, TPHL 48 15 ns RL Diff = 54 CL1 = CL2 = 100 pF, Figure 3 Driver O/P to O/P TSKEW 02 ns RL Diff = 54 CL1 = CL2 = 100 pF, Figure 3 Driver Rise/Fall Time TR, TF 510 ns RL Diff = 54 CL1 = CL2 = 100 pF, Figure 3 Driver Enable to Output Valid 8 15 ns Driver Disable Timing 8 15 ns RECEIVER Propagation Delay Input to Output TPLH, TPHL 812 20 ns CL = 15 pF, Figure 5 Skew |TPLH–TPHL|0 2 ns Receiver Enable TEN1 5 10 ns Figure 6 Receiver Disable TEN2 5 10 ns Figure 6 Specifications subject to change without notice. PRELIMINARY TECHNICAL DATA |
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