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ADM1032 Fiches technique(PDF) 2 Page - Analog Devices

No de pièce ADM1032
Description  -1C Remote and Local System Temperature Monitor
Download  12 Pages
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Fabricant  AD [Analog Devices]
Site Internet  http://www.analog.com
Logo AD - Analog Devices

ADM1032 Fiches technique(HTML) 2 Page - Analog Devices

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REV. 0
–2–
ADM1032–SPECIFICATIONS (T
A = TMIN to TMAX, VDD = VMIN to VMAX, unless otherwise noted.)
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
POWER SUPPLY
Supply Voltage, VDD
3.0
3.30
5.5
V
Average Operating Supply Current, ICC
170
215
µA
0.0625 Conversions/Sec Rate
1
5.5
10
µA
Standby Mode
Undervoltage Lockout Threshold
2.35
2.55
2.8
V
VDD Input, Disables ADC, Rising Edge
Power-On Reset Threshold
1
2.4
V
TEMPERATURE-TO-DIGITAL CONVERTER
Local Sensor Accuracy
±1
±3
°C0 ≤ T
A
≤ 100°C, V
CC = 3 V to 3.6 V
Resolution
1
°C
Remote Diode Sensor Accuracy
±1
°C60°C ≤ TD ≤ 100°C, VCC = 3 V to 3.6 V
±3
°C0°C ≤ T
D
≤ 120°C
Resolution
0.125
°C
Remote Sensor Source Current
230
µA
High Level, Note 2
13
µA
Low Level, Note 2
Conversion Time
35.7
142.8
ms
From Stop Bit to Conversion Complete
(Both Channels) One-Shot Mode with
Averaging Switched On
5.7
22.8
ms
One-Shot Mode with Averaging Off
(i.e., Conversion Rate = 32 or 64
Conversions per Second)
OPEN-DRAIN DIGITAL OUTPUTS
(
THERM, ALERT)
Output Low Voltage, VOL
0.4
V
IOUT = –6.0 mA
2
High Level Output Leakage Current, IOH
0.1
1
µAV
OUT = VDD
2
SMBus INTERFACE
2
Logic Input High Voltage, VIH
2.1
V
VDD = 3 V to 5.5 V
SCLK, SDATA
Logic Input Low Voltage, VIL
0.8
V
VDD = 3 V to 5.5 V
Hysteresis
500
mV
SCLK, SDATA
SMBus Output Low Sink Current
6
mA
SDATA Forced to 0.6 V
ALERT Output Low Sink Current
1
mA
ALERT Forced to 0.4 V
Logic Input Current, IIH, IIL
–1
+1
µA
SMBus Input Capacitance, SCLK, SDATA
5
pF
SMBus Clock Frequency
100
kHz
SMBus Timeout
25
64
ms
Note 3
SMBus Clock Low Time, tLOW
4.7
µstLOW between 10% Points
SMBus Clock High Time, tHIGH
4
µst
HIGH between 90% Points
SMBus Start Condition Setup Time, tSU:STA
4.7
µs
SMBus Start Condition Hold Time, tHD:STA
4
µs
Time from 10% of SDATA to 90%
of SCLK
SMBus Stop Condition Setup Time, tSU:STO
4
µs
Time from 90% of SCLK to 10%
of SDATA
SMBus Data Valid to SCLK Rising Edge
250
ns
Time for 10% or 90% of SDATA to
Time, tSU:DAT
10% of SCLK
SMBus Data Hold Time, tHD:DAT
300
µs
SMBus Bus Free Time, tBUF
4.7
µs
Between Start/Stop Condition
SCLK Falling Edge to SDATA
1
µs
Master Clocking in Data
Valid Time, tVD,DAT
SCLK, SDATA Rise Time, tR
1
µs
SCLK, SDATA Fall Time, tF
300
ns
NOTES
1See Table VI for information on other conversion rates.
2Guaranteed by Design, not production tested.
3The SMBus timeout is a programmable feature. By default it is not enabled. Details on how to enable it are available in the SMBus section of this data sheet.
Specifications subject to change without notice.


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