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AD9884AKS-140 Fiches technique(PDF) 10 Page - Analog Devices |
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AD9884AKS-140 Fiches technique(HTML) 10 Page - Analog Devices |
10 / 24 page REV. B AD9884A –10– INPUT GAIN 02 7–0 REDGAIN Red Channel Gain Adjust An 8-bit word that sets the gain of the RED channel. The AD9884A can accommodate input signals with a full-scale range of between 0.5 V and 1.0 V p-p. Setting REDGAIN to 255 corresponds to an input range of 1.0 V. A REDGAIN of 0 establishes an input range of 0.5 V. Note that increasing REDGAIN results in the picture having less contrast (the input signal uses fewer of the available converter codes). See Figure 8. The power-up default value is REDGAIN = 80h. 03 7–0 GRNGAIN Green Channel Gain Adjust An 8-bit word that sets the gain of the GREEN channel. See REDGAIN (02). The power-up default value is GRNGAIN = 80h. 04 7–0 BLUGAIN Blue Channel Gain Adjust An 8-bit word that sets the gain of the BLUE channel. See REDGAIN (02). The power-up default value is BLUGAIN = 80h. INPUT OFFSET 05 7–2 REDOFST Red Channel Offset Adjust A six-bit offset binary word that sets the dc offset of the RED channel. One LSB of offset adjustment equals approximately one LSB change in the ADC offset. Therefore, the absolute magnitude of the offset adjustment scales as the gain of the channel is changed (Figure 9). A nominal setting of 31 results in the channel nomi- nally clamping the back porch (during the clamping interval) to code 00. An offset setting of 63 results in the channel clamping to code 31 of the ADC. An offset setting of 0 clamps to code –31 (off the bottom of the range). Increasing the value of REDOFST decreases the brightness of the channel. The power-up default value is REDOFST = 80h. 06 7–2 GRNOFST Green Channel Offset Adjust A six-bit offset binary word that sets the dc offset of the GREEN channel. See REDOFST (05). The power-up default value is GRNOFST = 80h. 07 7–2 BLUOFST Blue Channel Offset Adjust A six-bit offset binary word that sets the DC offset of the GREEN channel. See REDOFST (05). The power-up default value is BLUOFST = 80h. CLAMP TIMING 08 7–0 CLPLACE Clamp Placement An 8-bit register that sets the position of the internally generated clamp. When EXTCLMP = 0, a clamp signal is generated internally, at a position established by CLPLACE and for a duration set by CLDUR. Clamping is started CLPLACE pixel periods after the trailing edge of HSYNC. CLPLACE may be programmed to any value between 1 and 255. CLPLACE = 0 is not supported. The clamp should be placed during a time that the input signal presents a stable black-level reference, usually the back porch period between HSYNC and the image. A value of 08h will usually work. When EXTCLMP = 1, this register is ignored. The power-up default value is CLPLACE = 80h. 09 7–0 CLDUR Clamp Duration An 8-bit register that sets the duration of the internally gener- ated clamp. When EXTCLMP = 0, a clamp signal is generated internally, at a position established by CLPLACE and for a duration set by CLDUR. Clamping is started CLPLACE pixel periods after the trailing edge of HSYNC, and continues for CLDUR pixel peri- ods. CLDUR may be programmed to any value between 1 and 255. CLDUR = 0 is not supported. For the best results, the clamp duration should be set to include the majority of the black reference signal time found following the HSYNC signal trailing edge. Insufficient clamping time can produce brightness changes at the top of the screen, and a slow recovery from large changes in the Average Picture Level (APL), or brightness. A value of 10h to 20h works with most standard signals. When EXTCLMP = 1, this register is ignored. The power-up default value is CLDUR = 80h. |
Numéro de pièce similaire - AD9884AKS-140 |
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Description similaire - AD9884AKS-140 |
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