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AD9777 Fiches technique(PDF) 1 Page - Analog Devices

No de pièce AD9777
Description  16-Bit, 160 MSPS 2X/4X/8X Interpolating Dual TxDAC D/A Converter
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Fabricant  AD [Analog Devices]
Site Internet  http://www.analog.com
Logo AD - Analog Devices

AD9777 Fiches technique(HTML) 1 Page - Analog Devices

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Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2002
AD9777*
16-Bit, 160 MSPS 2 /4 /8
Interpolating Dual TxDAC+® D/A Converter
FEATURES
16-Bit Resolution, 160/400 MSPS Input/Output Data Rate
Selectable 2 /4 /8
Interpolating Filter
Programmable Channel Gain and Offset Adjustment
fS/4, fS/8 Digital Quadrature Modulation
Capability
Direct IF Transmission Mode for 70 MHz + IFs
Enables Image Rejection Architecture
Fully Compatible SPI Port
Excellent AC Performance
SFDR –73 dBc @ 2 MHz–35 MHz
WCDMA ACPR 71 dB @ IF = 71 MHz
Internal PLL Clock Multiplier
Selectable Internal Clock Divider
Versatile Clock Input
Differential/Single-Ended Sine Wave or
TTL/CMOS/LVPECL Compatible
Versatile Input Data Interface
Two’s Complement/Straight Binary Data Coding
Dual-Port or Single-Port Interleaved Input Data
Single 3.3 V Supply Operation
Power Dissipation: Typical 1.2 W @ 3.3 V
On-Chip 1.2 V Reference
80-Lead Thermally Enhanced TQFP Package
FUNCTIONAL BLOCK DIAGRAM
DIFFERENTIAL
CLK
COS
SIN
HALF-
BAND
FILTER 1
16
IMAGE
REJECTION/
DUAL DAC
MODE
BYPASS
MUX
I AND Q
NONINTERLEAVED
OR
INTERLEAVED
DATA
WRITE
SELECT
CLOCK OUT
HALF-BAND FILTERS ALSO CAN BE
CONFIGURED FOR "ZERO STUFFING ONLY"
*
GAIN
DAC
OFFSET
DAC
fDAC/2, 4, 8
SIN
COS
I/Q DAC
GAIN/OFFSET
REGISTERS
(
fDAC)
PHASE DETECTOR
AND VCO
PRESCALER
PLL CLOCK MULTIPLIER AND CLOCK DIVIDER
16
16
/2
16
DATA
ASSEMBLER
16
16
16
16
16
16
MUX
CONTROL
/2
/2
I
LATCH
Q
LATCH
/2
HALF-
BAND
FILTER 2
HALF-
BAND
FILTER 3
**
*
AD9777
SPI INTERFACE AND
CONTROL REGISTERS
FILTER
BYPASS
MUX
IDAC
IDAC
IOUT
GENERAL DESCRIPTION
The AD9777 is the 16-bit member of the AD977x pin compatible,
high performance, programmable 2
×/4×/8× interpolating TxDAC+
family. The AD977x family features a serial port interface (SPI)
providing a high level of programmability, thus allowing for
enhanced system level options. These options include: selectable
2
×/4×/8× interpolation filters; fS/2, fS/4, or fS/8 digital quadrature
modulation with image rejection; a direct IF mode; programmable
channel gain and offset control; programmable internal clock
divider; straight binary or two’s complement data interface; and
a single-port or dual-port data interface.
The selectable 2
×/4×/8× interpolation filters simplify the require-
ments of the reconstruction filters while simultaneously enhancing
the TxDAC+ family’s pass-band noise/distortion performance.
The independent channel gain and offset adjust registers allow
the user to calibrate LO feedthrough and sideband suppression
(continued on page 2)
APPLICATIONS
Communications
Analog Quadrature Modulation Architectures
3G, Multicarrier GSM, TDMA, CDMA Systems
Broadband Wireless, Point-to-Point Microwave Radios
Instrumentation/ATE
TxDAC+ is a registered trademark of Analog Devices, Inc.
*Protected by U.S. Patent Numbers, 5568145, 5689257, and 5703519. Other patents pending.


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