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AD8403AN100 Fiches technique(PDF) 3 Page - Analog Devices

No de pièce AD8403AN100
Description  1-/2-/4-Channel Digital Potentiometers
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Fabricant  AD [Analog Devices]
Site Internet  http://www.analog.com
Logo AD - Analog Devices

AD8403AN100 Fiches technique(HTML) 3 Page - Analog Devices

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50 k
& 100 k
VERSION
ELECTRICAL CHARACTERISTICS
Parameter
Symbol
Conditions
Min
Typ
1
Max
Units
DC CHARACTERISTICS RHEOSTAT MODE Specifications Apply to All VRs
Resistor Differential NL
2
R-DNL
RWB, VA = NC
–1
±1/4
+1
LSB
Resistor Nonlinearity2
R-INL
RWB, VA = NC
–2
±1/2
+2
LSB
Nominal Resistance
3
RTA = +25
°C, Model: AD840XYY50
35
50
65
k
RTA = +25°C, Model: AD840XYY100
70
100
130
k
Resistance Tempco
∆R
AB/∆TVAB = VDD, Wiper = No Connect
500
ppm/
°C
Wiper Resistance
RW
IW = 1 V/R
53
100
Nominal Resistance Match
∆R/R
O
CH 1 to 2, 3, or 4, VAB = VDD, TA = +25°C
0.2
1
%
DC CHARACTERISTICS POTENTIOMETER DIVIDER Specifications Apply to All VRs
Resolution
N
8
Bits
Integral Nonlinearity
4
INL
–4
±1
+4
LSB
Differential Nonlinearity
4
DNL
VDD = +5 V
–1
±1/4
+1
LSB
DNL
VDD = +3 V
TA = +25
°C–1
±1/4
+1
LSB
DNL
VDD = +3 V
TA = –40
°C, +85°C
–1.5
±1/2
+1.5
LSB
Voltage Divider Tempco
∆V
W/∆T
Code = 80H
15
ppm/
°C
Full-Scale Error
VWFSE
Code = FFH
–1
–0.25
0
LSB
Zero-Scale Error
VWZSE
Code = 00H
0
+0.1
+1
LSB
RESISTOR TERMINALS
Voltage Range5
VA, B, W
0VDD
V
Capacitance
6 Ax, Bx
CA, B
f = 1 MHz, Measured to GND, Code = 80H
15
pF
Capacitance
6 Wx
CW
f = 1 MHz, Measured to GND, Code = 80H
80
pF
Shutdown Current7
IA_SD
VA = VDD, VB = 0 V, SHDN = 0
0.01
5
µA
Shutdown Wiper Resistance
RW_SD
VA = VDD, VB = 0 V, SHDN = 0, VDD = +5 V
100
200
DIGITAL INPUTS & OUTPUTS
Input Logic High
VIH
VDD = +5 V
2.4
V
Input Logic Low
VIL
VDD = +5 V
0.8
V
Input Logic High
VIH
VDD = +3 V
2.1
V
Input Logic Low
VIL
VDD = +3 V
0.6
V
Output Logic High
VOH
RL = 1 kΩ to VDD
VDD–0.1
V
Output Logic Low
VOL
IOL = 1.6 mA, VDD = +5 V
0.4
V
Input Current
IIL
VIN = 0 V or +5 V, VDD = +5 V
±1
µA
Input Capacitance6
CIL
5pF
POWER SUPPLIES
Power Supply Range
VDD Range
2.7
5.5
V
Supply Current (CMOS)
IDD
VIH = VDD or VIL = 0 V
0.01
5
µA
Supply Current (TTL)8
IDD
VIH = 2.4 V or 0.8 V, VDD = +5.5 V
0.9
4
mA
Power Dissipation (CMOS)
9
PDISS
VIH = VDD or VIL = 0 V, VDD = +5.5 V
27.5
µW
Power Supply Sensitivity
PSS
VDD = +5 V ± 10%
0.0002 0.001
%/%
PSS
VDD = +3 V ± 10%
0.006
0.03
%/%
DYNAMIC CHARACTERISTICS6, 10
Bandwidth –3 dB
BW_50K
R = 50 k
125
kHz
BW_100K
R = 100 k
71
kHz
Total Harmonic Distortion
THDW
VA = 1 V rms + 2 V dc, VB = 2 V dc, f = 1 kHz
0.003
%
VW Settling Time
tS_50K
VA = VDD, VB = 0 V,
±1% Error Band
9
µs
tS_100K
VA = VDD, VB = 0 V, ± 1% Error Band
18
µs
Resistor Noise Voltage
eNWB_50K
RWB = 25 kΩ, f = 1 kHz, RS = 0
20
nV/
√Hz
eNWB_100K
RWB = 50 k
Ω, f = 1 kHz, RS = 0
29
nV/
√Hz
Crosstalk
11
CT
VA = VDD, VB = 0 V
–65
dB
NOTES FOR 50 k
Ω and 100 kΩ VERSIONS
1 Typicals represent average readings at +25
°C and V
DD = +5 V.
2 Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. See Figure 30 test circuit.
IW = VDD/R for VDD = +3 V or +5 V for the 50 kΩ and 100 kΩ versions.
3 V
AB = VDD, Wiper (VW) = No Connect.
4 INL and DNL are measured at V
W with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. V A = VDD and VB = 0 V.
DNL Specification limits of
± 1 LSB maximum are Guaranteed Monotonic operating conditions. See Figure 29 test circuit.
5 Resistor terminals A, B, W have no limitations on polarity with respect to each other.
6 Guaranteed by design and not subject to production test. Resistor-terminal capacitance tests are measured with 2.5 V bias on the measured terminal. The remaining
resistor terminals are left open circuit.
7 Measured at the Ax terminals. All Ax terminals are open circuited in shutdown mode.
8 Worst case supply current consumed when input logic level at 2.4 V, standard characteristic of CMOS logic. See Figure 21 for a plot of I
DD versus logic voltage.
9 P
DISS is calculated from (IDD × VDD). CMOS logic level inputs result in minimum power dissipation.
10 All Dynamic Characteristics use V
DD = +5 V.
11 Measured at a V
W pin where an adjacent VW pin is making a full-scale voltage change.
Specifications subject to change without notice.
AD8400/AD8402/AD8403
REV. B
–3–
(VDD = +3 V
10% or + 5 V
10%, VA = +VDD, VB = 0 V, –40 C ≤ TA ≤ +85 C unless
otherwise noted)
SPECIFICATIONS


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