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AD7853AR Fiches technique(PDF) 6 Page - Analog Devices

No de pièce AD7853AR
Description  3 V to 5 V Single Supply, 200 kSPS 12-Bit Sampling ADCs
Download  34 Pages
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Fabricant  AD [Analog Devices]
Site Internet  http://www.analog.com
Logo AD - Analog Devices

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REV. B
–6–
AD7853/AD7853L
ABSOLUTE MAXIMUM RATINGS
1
(TA = +25°C unless otherwise noted)
AVDD to AGND . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
DVDD to DGND . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
AVDD to DVDD . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V
Analog Input Voltage to AGND . . . . –0.3 V to AVDD + 0.3 V
Digital Input Voltage to DGND . . . . –0.3 V to DVDD + 0.3 V
Digital Output Voltage to DGND . . . –0.3 V to DVDD + 0.3 V
REFIN/REFOUT to AGND . . . . . . . . . –0.3 V to AVDD + 0.3 V
Input Current to Any Pin Except Supplies
2 . . . . . . . .
±10 mA
Operating Temperature Range
Commercial (A, B Versions) . . . . . . . . . . . –40
°C to +85°C
Storage Temperature Range . . . . . . . . . . . –65
°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . +150
°C
Plastic DIP Package, Power Dissipation . . . . . . . . . . 450 mW
θ
JA Thermal Impedance
. . . . . . . . . . . . . . . . . . . . . 105
°C/W
θ
JC Thermal Impedance . . . . . . . . . . . . . . . . . . . .
34.7
°C/W
Lead Temperature, (Soldering, 10 sec) . . . . . . . . . . +260
°C
SOIC, SSOP Package, Power Dissipation . . . . . . . . . 450 mW
θ
JA Thermal Impedance . . . 75°C/W (SOIC) 115°C/W (SSOP)
θ
JC Thermal Impedance . . . . 25
°C/W (SOIC) 35°C/W (SSOP)
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . +215
°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . +220
°C
ESD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . >3 kV
NOTES
1Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
2Transient currents of up to 100 mA will not cause SCR latch-up.
ORDERING GUIDE
Linearity
Power
Error
Dissipation
Package
Model
(LSB)
1
(mW)
Options
2
AD7853AN
±1
20
N-24
AD7853BN
±1/2
20
N-24
AD7853LAN
3
±1
6.85
N-24
AD7853LBN
3
±1
6.85
N-24
AD7853AR
±1
20
R-24
AD7853BR
±1/2
20
R-24
AD7853LAR
3
±1
6.85
R-24
AD7853LBR
3
±1
6.85
R-24
AD7853ARS
±1
6.85
RS-24
AD7853LARS
3
±1
6.85
RS-24
EVAL-AD7853CB
4
EVAL-CONTROL BOARD
5
NOTES
1Linearity error refers to the integral linearity error.
2N = Plastic DIP; R = SOIC; RS = SSOP.
3L signifies the low power version.
4This can be used as a stand-alone evaluation board or in conjunction with the
EVAL-CONTROL BOARD for evaluation/demonstration purposes.
5This board is a complete unit allowing a PC to control and communicate with
all Analog Devices, Inc. evaluation boards ending in the CB designators.
PIN CONFIGURATIONS
DIP, SOIC AND SSOP
CAL
SCLK
SM2
SLEEP
REFIN/REFOUT
BUSY
AIN(+)
AVDD
AGND
CREF1
CREF2
AIN(–)
CONVST
DVDD
SYNC
1
2
3
7
24
23
22
21
20
19
18
17
16
15
14
13
8
9
10
11
12
4
5
6
CLKIN
DIN
DOUT
DGND
AMODE
POLARITY
SM1
NC
AGND
NC = NO CONNECT
TOP VIEW
(Not to Scale)
AD7853/53L


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